| Message ID | 20241025060136.9884-4-suraj.kandpal@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add 6k resolution support for a single CRTC | expand |
On Fri, Oct 25, 2024 at 11:31:34AM +0530, Suraj Kandpal wrote: > Increase the psr max_h limit to 4096. Commit message doesn't match code (this should probably say max_v instead of max_h). Since PSR2 size is supported up to the maximum pipe size now (for both Xe2 and Xe3) would it be simpler to just make the check on psr_max_{h,v} conditional to pre-Xe2? Then if we don't have any truly PSR-specific limits, we don't need to keep duplicating the pipe limits in two places going forward. Matt > > Bspec: 69885, 68858 > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c > index 4176163ec19a..c22386a31a63 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -1453,7 +1453,11 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > return false; > } > > - if (DISPLAY_VER(display) >= 12) { > + if (DISPLAY_VER(display) >= 20) { > + psr_max_h = 5120; > + psr_max_v = 4096; > + max_bpp = 30; > + } else if (DISPLAY_VER(display) >= 12) { > psr_max_h = 5120; > psr_max_v = 3200; > max_bpp = 30; > -- > 2.34.1 >
> -----Original Message----- > From: Roper, Matthew D <matthew.d.roper@intel.com> > Sent: Saturday, October 26, 2024 3:31 AM > To: Kandpal, Suraj <suraj.kandpal@intel.com> > Cc: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; Nautiyal, > Ankit K <ankit.k.nautiyal@intel.com> > Subject: Re: [PATCH 3/5] drm/i915/psr: Increase psr size limits for Xe2 > > On Fri, Oct 25, 2024 at 11:31:34AM +0530, Suraj Kandpal wrote: > > Increase the psr max_h limit to 4096. > > Commit message doesn't match code (this should probably say max_v > instead of max_h). Sure will fix that > > Since PSR2 size is supported up to the maximum pipe size now (for both > Xe2 and Xe3) would it be simpler to just make the check on psr_max_{h,v} > conditional to pre-Xe2? Then if we don't have any truly PSR-specific limits, we > don't need to keep duplicating the pipe limits in two places going forward. > if we @Hogander, Jouni do you see any risk of this being done or should we go ahead with Matt said And have the checks just for pre-Xe2 Regards, Suraj Kandpal > > Matt > > > > > Bspec: 69885, 68858 > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_psr.c | 6 +++++- > > 1 file changed, 5 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > b/drivers/gpu/drm/i915/display/intel_psr.c > > index 4176163ec19a..c22386a31a63 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > @@ -1453,7 +1453,11 @@ static bool intel_psr2_config_valid(struct > intel_dp *intel_dp, > > return false; > > } > > > > - if (DISPLAY_VER(display) >= 12) { > > + if (DISPLAY_VER(display) >= 20) { > > + psr_max_h = 5120; > > + psr_max_v = 4096; > > + max_bpp = 30; > > + } else if (DISPLAY_VER(display) >= 12) { > > psr_max_h = 5120; > > psr_max_v = 3200; > > max_bpp = 30; > > -- > > 2.34.1 > > > > -- > Matt Roper > Graphics Software Engineer > Linux GPU Platform Enablement > Intel Corporation
> -----Original Message----- > From: Roper, Matthew D <matthew.d.roper@intel.com> > Sent: Saturday, October 26, 2024 3:31 AM > To: Kandpal, Suraj <suraj.kandpal@intel.com> > Cc: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; Nautiyal, > Ankit K <ankit.k.nautiyal@intel.com> > Subject: Re: [PATCH 3/5] drm/i915/psr: Increase psr size limits for Xe2 > > On Fri, Oct 25, 2024 at 11:31:34AM +0530, Suraj Kandpal wrote: > > Increase the psr max_h limit to 4096. > > Commit message doesn't match code (this should probably say max_v > instead of max_h). > > Since PSR2 size is supported up to the maximum pipe size now (for both > Xe2 and Xe3) would it be simpler to just make the check on psr_max_{h,v} > conditional to pre-Xe2? Then if we don't have any truly PSR-specific limits, we > don't need to keep duplicating the pipe limits in two places going forward. Also the reason we may continue to need the ladder of checks here is that when we check The limits in intel_display we check it considering the num of joined pipes which not only changes width But also the height to 4320 instead of 4096 which means we need to get these limits separately checked here As well Regards, Suraj Kandpal > > > Matt > > > > > Bspec: 69885, 68858 > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_psr.c | 6 +++++- > > 1 file changed, 5 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > b/drivers/gpu/drm/i915/display/intel_psr.c > > index 4176163ec19a..c22386a31a63 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > @@ -1453,7 +1453,11 @@ static bool intel_psr2_config_valid(struct > intel_dp *intel_dp, > > return false; > > } > > > > - if (DISPLAY_VER(display) >= 12) { > > + if (DISPLAY_VER(display) >= 20) { > > + psr_max_h = 5120; > > + psr_max_v = 4096; > > + max_bpp = 30; > > + } else if (DISPLAY_VER(display) >= 12) { > > psr_max_h = 5120; > > psr_max_v = 3200; > > max_bpp = 30; > > -- > > 2.34.1 > > > > -- > Matt Roper > Graphics Software Engineer > Linux GPU Platform Enablement > Intel Corporation
On Mon, 2024-10-28 at 03:51 +0000, Kandpal, Suraj wrote: > > > > -----Original Message----- > > From: Roper, Matthew D <matthew.d.roper@intel.com> > > Sent: Saturday, October 26, 2024 3:31 AM > > To: Kandpal, Suraj <suraj.kandpal@intel.com> > > Cc: intel-xe@lists.freedesktop.org; > > intel-gfx@lists.freedesktop.org; Nautiyal, > > Ankit K <ankit.k.nautiyal@intel.com> > > Subject: Re: [PATCH 3/5] drm/i915/psr: Increase psr size limits for > > Xe2 > > > > On Fri, Oct 25, 2024 at 11:31:34AM +0530, Suraj Kandpal wrote: > > > Increase the psr max_h limit to 4096. > > > > Commit message doesn't match code (this should probably say max_v > > instead of max_h). > > Sure will fix that > > > > > Since PSR2 size is supported up to the maximum pipe size now (for > > both > > Xe2 and Xe3) would it be simpler to just make the check on > > psr_max_{h,v} > > conditional to pre-Xe2? Then if we don't have any truly PSR- > > specific limits, we > > don't need to keep duplicating the pipe limits in two places going > > forward. > > if we > > @Hogander, Jouni do you see any risk of this being done or should we > go ahead with Matt said > And have the checks just for pre-Xe2 I think you should modify it as Matt suggested. Your concern on joiner in latter mail is not valid. Bspec says: "PSR2 is supported up to the maximum pipe active size." and PSR2 should work with joiner as well tought currently it is disabled. That is another topic and not related to this. BR, Jouni Högander > > Regards, > Suraj Kandpal > > > > > Matt > > > > > > > > Bspec: 69885, 68858 > > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_psr.c | 6 +++++- > > > 1 file changed, 5 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > > b/drivers/gpu/drm/i915/display/intel_psr.c > > > index 4176163ec19a..c22386a31a63 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > > @@ -1453,7 +1453,11 @@ static bool intel_psr2_config_valid(struct > > intel_dp *intel_dp, > > > return false; > > > } > > > > > > - if (DISPLAY_VER(display) >= 12) { > > > + if (DISPLAY_VER(display) >= 20) { > > > + psr_max_h = 5120; > > > + psr_max_v = 4096; > > > + max_bpp = 30; > > > + } else if (DISPLAY_VER(display) >= 12) { > > > psr_max_h = 5120; > > > psr_max_v = 3200; > > > max_bpp = 30; > > > -- > > > 2.34.1 > > > > > > > -- > > Matt Roper > > Graphics Software Engineer > > Linux GPU Platform Enablement > > Intel Corporation
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 4176163ec19a..c22386a31a63 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1453,7 +1453,11 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } - if (DISPLAY_VER(display) >= 12) { + if (DISPLAY_VER(display) >= 20) { + psr_max_h = 5120; + psr_max_v = 4096; + max_bpp = 30; + } else if (DISPLAY_VER(display) >= 12) { psr_max_h = 5120; psr_max_v = 3200; max_bpp = 30;
Increase the psr max_h limit to 4096. Bspec: 69885, 68858 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)