diff mbox series

[4/5] drm/i915/xe3lpd: Increase max_h max_v for PSR

Message ID 20241025060136.9884-5-suraj.kandpal@intel.com (mailing list archive)
State New
Headers show
Series Add 6k resolution support for a single CRTC | expand

Commit Message

Kandpal, Suraj Oct. 25, 2024, 6:01 a.m. UTC 
Spec states that PSR max active is same as max pipe active values.
Now that each pipe supports 6k resolution increasing max_h and
max_v for PSR too.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index c22386a31a63..a358beb39846 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1453,7 +1453,11 @@  static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
-	if (DISPLAY_VER(display) >= 20) {
+	if (DISPLAY_VER(dev_priv) >= 30) {
+		psr_max_h = 6144;
+		psr_max_v = 4096;
+		max_bpp = 30;
+	} else if (DISPLAY_VER(display) >= 20) {
 		psr_max_h = 5120;
 		psr_max_v = 4096;
 		max_bpp = 30;