Message ID | 20241027134557.862036-3-ankit.k.nautiyal@intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Add support for 3 VDSC engines 12 slices | expand |
On 10/27/2024 7:15 PM, Ankit Nautiyal wrote: > At the moment dsc_split represents whether the dsc splitter is used > or not. With 3 DSC engines, the splitter can split into two streams > or three streams. > > Instead of representing the splitter's state, it is more effective to > represent the number of DSC streams per pipe. > > Replace the `dsc.dsc_split` member with `dsc.num_streams` to indicate the > number of DSC streams used per pipe. This change will implicitly > convey the splitter's operation mode. > > v2: Avoid new enum for dsc split. (Suraj) > v3: > -Replace dsc_split with num_stream. (Suraj) > -Avoid extra parentheses. (Jani) > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> > --- > drivers/gpu/drm/i915/display/icl_dsi.c | 4 +++- > drivers/gpu/drm/i915/display/intel_display.c | 2 +- > .../gpu/drm/i915/display/intel_display_types.h | 2 +- > drivers/gpu/drm/i915/display/intel_dp.c | 4 +++- > drivers/gpu/drm/i915/display/intel_vdsc.c | 16 +++++++++++----- > 5 files changed, 19 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c > index 115d79c80b9a..b01dfbeb314b 100644 > --- a/drivers/gpu/drm/i915/display/icl_dsi.c > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c > @@ -1596,7 +1596,9 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, > > /* FIXME: split only when necessary */ > if (crtc_state->dsc.slice_count > 1) > - crtc_state->dsc.dsc_split = true; > + crtc_state->dsc.num_streams = 2; > + else > + crtc_state->dsc.num_streams = 1; > > /* FIXME: initialize from VBT */ > vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index ef1436146325..3dfff0a8c386 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -5741,7 +5741,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, > PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset); > > PIPE_CONF_CHECK_BOOL(dsc.compression_enable); > - PIPE_CONF_CHECK_BOOL(dsc.dsc_split); > + PIPE_CONF_CHECK_I(dsc.num_streams); > PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16); > > PIPE_CONF_CHECK_BOOL(splitter.enable); > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > index 2bb1fa64da2f..5611a4dd6a6f 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1235,7 +1235,7 @@ struct intel_crtc_state { > /* Display Stream compression state */ > struct { > bool compression_enable; > - bool dsc_split; > + int num_streams; > /* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */ > u16 compressed_bpp_x16; > u8 slice_count; > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index bd9f37e1a13f..dbb1d75c0576 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -2410,7 +2410,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, > * then we need to use 2 VDSC instances. > */ > if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1) > - pipe_config->dsc.dsc_split = true; > + pipe_config->dsc.num_streams = 2; > + else > + pipe_config->dsc.num_streams = 1; > > ret = intel_dp_dsc_compute_params(connector, pipe_config); > if (ret < 0) { > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c > index 40525f5c4c42..afc40d180dec 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c > @@ -379,7 +379,7 @@ intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder) > > static int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state) > { > - return crtc_state->dsc.dsc_split ? 2 : 1; > + return crtc_state->dsc.num_streams; > } > > int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state) > @@ -976,8 +976,14 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) > if (!crtc_state->dsc.compression_enable) > goto out; > > - crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) && > - (dss_ctl1 & JOINER_ENABLE); > + if (dss_ctl1 & JOINER_ENABLE) { > + if (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) > + crtc_state->dsc.num_streams = 2; > + else > + crtc_state->dsc.num_streams = 1; > + } else { > + crtc_state->dsc.num_streams = 0; I realized that this is a mistake, num_streams cannot be 0 when dsc.compression_enable is set. Will correct this to num_streams = 1, and simplify the if-else block. Regards, Ankit > + } > > intel_dsc_get_pps_config(crtc_state); > out: > @@ -988,10 +994,10 @@ static void intel_vdsc_dump_state(struct drm_printer *p, int indent, > const struct intel_crtc_state *crtc_state) > { > drm_printf_indent(p, indent, > - "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, split: %s\n", > + "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, num_streams: %d\n", > FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16), > crtc_state->dsc.slice_count, > - str_yes_no(crtc_state->dsc.dsc_split)); > + crtc_state->dsc.num_streams); > } > > void intel_vdsc_state_dump(struct drm_printer *p, int indent,
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 115d79c80b9a..b01dfbeb314b 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -1596,7 +1596,9 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, /* FIXME: split only when necessary */ if (crtc_state->dsc.slice_count > 1) - crtc_state->dsc.dsc_split = true; + crtc_state->dsc.num_streams = 2; + else + crtc_state->dsc.num_streams = 1; /* FIXME: initialize from VBT */ vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ef1436146325..3dfff0a8c386 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5741,7 +5741,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset); PIPE_CONF_CHECK_BOOL(dsc.compression_enable); - PIPE_CONF_CHECK_BOOL(dsc.dsc_split); + PIPE_CONF_CHECK_I(dsc.num_streams); PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16); PIPE_CONF_CHECK_BOOL(splitter.enable); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 2bb1fa64da2f..5611a4dd6a6f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1235,7 +1235,7 @@ struct intel_crtc_state { /* Display Stream compression state */ struct { bool compression_enable; - bool dsc_split; + int num_streams; /* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */ u16 compressed_bpp_x16; u8 slice_count; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index bd9f37e1a13f..dbb1d75c0576 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2410,7 +2410,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, * then we need to use 2 VDSC instances. */ if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1) - pipe_config->dsc.dsc_split = true; + pipe_config->dsc.num_streams = 2; + else + pipe_config->dsc.num_streams = 1; ret = intel_dp_dsc_compute_params(connector, pipe_config); if (ret < 0) { diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 40525f5c4c42..afc40d180dec 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -379,7 +379,7 @@ intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder) static int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state) { - return crtc_state->dsc.dsc_split ? 2 : 1; + return crtc_state->dsc.num_streams; } int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state) @@ -976,8 +976,14 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) if (!crtc_state->dsc.compression_enable) goto out; - crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) && - (dss_ctl1 & JOINER_ENABLE); + if (dss_ctl1 & JOINER_ENABLE) { + if (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) + crtc_state->dsc.num_streams = 2; + else + crtc_state->dsc.num_streams = 1; + } else { + crtc_state->dsc.num_streams = 0; + } intel_dsc_get_pps_config(crtc_state); out: @@ -988,10 +994,10 @@ static void intel_vdsc_dump_state(struct drm_printer *p, int indent, const struct intel_crtc_state *crtc_state) { drm_printf_indent(p, indent, - "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, split: %s\n", + "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, num_streams: %d\n", FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16), crtc_state->dsc.slice_count, - str_yes_no(crtc_state->dsc.dsc_split)); + crtc_state->dsc.num_streams); } void intel_vdsc_state_dump(struct drm_printer *p, int indent,