@@ -1057,7 +1057,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
intel_ddi_disable_transcoder_func(old_crtc_state);
- if (DISPLAY_VER(dev_priv) >= 30 && !last_mst_stream)
+ if (DISPLAY_VER(dev_priv) >= 13 && !last_mst_stream)
intel_ddi_config_transcoder_dp2(encoder, old_crtc_state, false);
for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {
@@ -1227,7 +1227,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream)
intel_ddi_enable_transcoder_clock(encoder, pipe_config);
- if (DISPLAY_VER(dev_priv) >= 30 && !first_mst_stream) {
+ if (DISPLAY_VER(dev_priv) >= 13 && !first_mst_stream) {
intel_ddi_config_transcoder_dp2(encoder, pipe_config, true);
intel_ddi_config_transcoder_func(encoder, pipe_config);
}
On ADLP+ during modeset enabling configure the DDI function without enabling it for MST slave transcoders before programming the data and link M/N values. The DDI function gets enabled separately later in the transcoder enabling sequence. Also for these platforms the DP2 configuration needs to be enabled/disabled during enabling/disabling MST slave transcoders. Align the code with the spec wrt. the above DDI function and DP2 configuration programming. Bspec: 55424, 54128, 65448, 68849 Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)