diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index a2c528d707f4..21e5fad90a13 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -181,7 +181,7 @@ void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
 	crtc_state->cpu_transcoder = INVALID_TRANSCODER;
 	crtc_state->master_transcoder = INVALID_TRANSCODER;
 	crtc_state->hsw_workaround_pipe = INVALID_PIPE;
-	crtc_state->scaler_state.scaler_id = -1;
+	crtc_state->pch_pfit.scaler_id = -1;
 	crtc_state->mst_master_transcoder = INVALID_TRANSCODER;
 	crtc_state->max_link_bpp_x16 = INT_MAX;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 705ec5ad385c..c83c49d86ef5 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -320,10 +320,10 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 		   pipe_config->linetime, pipe_config->ips_linetime);
 
 	if (DISPLAY_VER(i915) >= 9)
-		drm_printf(&p, "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d, scaling_filter: %d\n",
+		drm_printf(&p, "num_scalers: %d, scaler_users: 0x%x, pfit scaler_id: %d, scaling_filter: %d\n",
 			   crtc->num_scalers,
 			   pipe_config->scaler_state.scaler_users,
-			   pipe_config->scaler_state.scaler_id,
+			   pipe_config->pch_pfit.scaler_id,
 			   pipe_config->hw.scaling_filter);
 
 	if (HAS_GMCH(i915))
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index dce3a20fa69f..a90d3a63dee9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5628,8 +5628,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 
 		PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
 		PIPE_CONF_CHECK_RECT(pch_pfit.dst);
+		PIPE_CONF_CHECK_I(pch_pfit.scaler_id);
 
-		PIPE_CONF_CHECK_I(scaler_state.scaler_id);
 		PIPE_CONF_CHECK_I(pixel_rate);
 
 		PIPE_CONF_CHECK_X(gamma_mode);
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 11aff485d8fa..febf3e5fb5cc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -449,7 +449,7 @@ static void intel_scaler_info(struct seq_file *m, struct intel_crtc *crtc)
 		seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d scaling_filter=%d",
 			   num_scalers,
 			   crtc_state->scaler_state.scaler_users,
-			   crtc_state->scaler_state.scaler_id,
+			   crtc_state->pch_pfit.scaler_id,
 			   crtc_state->hw.scaling_filter);
 
 		for (i = 0; i < num_scalers; i++) {
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e63a1d23316c..8269331f33b7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -724,9 +724,6 @@ struct intel_crtc_scaler_state {
 	 */
 #define SKL_CRTC_INDEX 31
 	unsigned scaler_users;
-
-	/* scaler used by crtc for panel fitting purpose */
-	int scaler_id;
 };
 
 /* {crtc,crtc_state}->mode_flags */
@@ -1126,6 +1123,10 @@ struct intel_crtc_state {
 	/* Panel fitter placement and size for Ironlake+ */
 	struct {
 		struct drm_rect dst;
+
+		/* pipe scaler (skl+) */
+		int scaler_id;
+
 		bool enabled;
 		bool force_thru;
 	} pch_pfit;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 880ea845207f..e8c2c4e7e585 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2519,7 +2519,7 @@ static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state
  */
 static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state)
 {
-	if (crtc_state->scaler_state.scaler_id >= 0)
+	if (crtc_state->pch_pfit.scaler_id >= 0)
 		return false;
 
 	return true;
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index e29e29c4cbc3..e5f566e323a0 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -249,7 +249,7 @@ int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
 	}
 	return skl_update_scaler(crtc_state, !crtc_state->hw.active,
 				 SKL_CRTC_INDEX,
-				 &crtc_state->scaler_state.scaler_id,
+				 &crtc_state->pch_pfit.scaler_id,
 				 drm_rect_width(&crtc_state->pipe_src),
 				 drm_rect_height(&crtc_state->pipe_src),
 				 width, height, NULL, 0,
@@ -436,7 +436,7 @@ static int setup_crtc_scaler(struct intel_atomic_state *state,
 	return intel_atomic_setup_scaler(scaler_state,
 					 hweight32(scaler_state->scaler_users),
 					 crtc, "CRTC", crtc->base.base.id,
-					 NULL, &scaler_state->scaler_id);
+					 NULL, &crtc_state->pch_pfit.scaler_id);
 }
 
 static int setup_plane_scaler(struct intel_atomic_state *state,
@@ -669,7 +669,7 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
 		return;
 
 	if (drm_WARN_ON(display->drm,
-			crtc_state->scaler_state.scaler_id < 0))
+			crtc_state->pch_pfit.scaler_id < 0))
 		return;
 
 	drm_rect_init(&src, 0, 0,
@@ -682,7 +682,7 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
 	uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
 	uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
 
-	id = scaler_state->scaler_id;
+	id = crtc_state->pch_pfit.scaler_id;
 
 	ps_ctrl = PS_SCALER_EN | PS_BINDING_PIPE | scaler_state->scalers[id].mode |
 		skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0);
@@ -832,7 +832,7 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state)
 		break;
 	}
 
-	scaler_state->scaler_id = id;
+	crtc_state->pch_pfit.scaler_id = id;
 	if (id >= 0)
 		scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
 	else
