| Message ID | 20241105071600.235338-6-vinod.govindapillai@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | use hw support for min/interim ddb allocation for async flip | expand |
On Tue, 05 Nov 2024, Vinod Govindapillai <vinod.govindapillai@intel.com> wrote: > Use intel_display object instead of struct drm_i915_private in > skl_plane_wm_equals(). This is in preparation for the rest of > the patches in this series where hw support for the minimum and > interim ddb allocations for async flip is added > > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> > --- > drivers/gpu/drm/i915/display/skl_watermark.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c > index 2018abc35c8a..a01b1dc01348 100644 > --- a/drivers/gpu/drm/i915/display/skl_watermark.c > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c > @@ -2384,13 +2384,13 @@ static bool skl_wm_level_equals(const struct skl_wm_level *l1, > l1->blocks == l2->blocks; > } > > -static bool skl_plane_wm_equals(struct drm_i915_private *i915, > +static bool skl_plane_wm_equals(struct intel_display *display, > const struct skl_plane_wm *wm1, > const struct skl_plane_wm *wm2) > { > int level; > > - for (level = 0; level < i915->display.wm.num_levels; level++) { > + for (level = 0; level < display->wm.num_levels; level++) { > /* > * We don't check uv_wm as the hardware doesn't actually > * use it. It only gets used for calculating the required > @@ -2650,7 +2650,7 @@ skl_print_wm_changes(struct intel_atomic_state *state) > old_wm = &old_pipe_wm->planes[plane_id]; > new_wm = &new_pipe_wm->planes[plane_id]; > > - if (skl_plane_wm_equals(i915, old_wm, new_wm)) > + if (skl_plane_wm_equals(&i915->display, old_wm, new_wm)) Please don't use "&i915->display" inline.c > continue; > > drm_dbg_kms(&i915->drm,
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 2018abc35c8a..a01b1dc01348 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -2384,13 +2384,13 @@ static bool skl_wm_level_equals(const struct skl_wm_level *l1, l1->blocks == l2->blocks; } -static bool skl_plane_wm_equals(struct drm_i915_private *i915, +static bool skl_plane_wm_equals(struct intel_display *display, const struct skl_plane_wm *wm1, const struct skl_plane_wm *wm2) { int level; - for (level = 0; level < i915->display.wm.num_levels; level++) { + for (level = 0; level < display->wm.num_levels; level++) { /* * We don't check uv_wm as the hardware doesn't actually * use it. It only gets used for calculating the required @@ -2650,7 +2650,7 @@ skl_print_wm_changes(struct intel_atomic_state *state) old_wm = &old_pipe_wm->planes[plane_id]; new_wm = &new_pipe_wm->planes[plane_id]; - if (skl_plane_wm_equals(i915, old_wm, new_wm)) + if (skl_plane_wm_equals(&i915->display, old_wm, new_wm)) continue; drm_dbg_kms(&i915->drm,
Use intel_display object instead of struct drm_i915_private in skl_plane_wm_equals(). This is in preparation for the rest of the patches in this series where hw support for the minimum and interim ddb allocations for async flip is added Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> --- drivers/gpu/drm/i915/display/skl_watermark.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)