diff mbox series

[17/23] drm/i915/display: Enable MSA Ignore Timing PAR only when in not fixed_rr mode

Message ID 20241111091221.2992818-18-ankit.k.nautiyal@intel.com (mailing list archive)
State New
Headers show
Series Use VRR timing generator for fixed refresh rate modes | expand

Commit Message

Nautiyal, Ankit K Nov. 11, 2024, 9:12 a.m. UTC 
MSA Ignore Timing PAR enable is set in the DP sink when we enable variable
refresh rate. When using VRR timing generator for fixed refresh rate
we do not want to ignore the mode timings, as the refresh rate is still
fixed. Modify the checks to enable MSA Ignore Timing PAR only when not
in fixed_rr mode.

v2: Initialize enable_msa_timing_par_ignore to false.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c              | 2 +-
 drivers/gpu/drm/i915/display/intel_dp_link_training.c | 8 +++++++-
 2 files changed, 8 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3c0640efde21..33ecd2a13016 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2230,7 +2230,7 @@  static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 
-	if (!crtc_state->vrr.tg_enable)
+	if (!crtc_state->vrr.tg_enable || crtc_state->vrr.mode == INTEL_VRRTG_MODE_FIXED_RR)
 		return;
 
 	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 397cc4ebae52..193c906f36a3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -726,8 +726,14 @@  void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, b
 static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
 					    const struct intel_crtc_state *crtc_state)
 {
+	bool enable_msa_timing_par_ignore = false;
+
+	/* Enable MSA TIMING PAR IGNORE only in non fixed_rr mode */
+	if (crtc_state->vrr.flipline && crtc_state->vrr.mode != INTEL_VRRTG_MODE_FIXED_RR)
+		enable_msa_timing_par_ignore = true;
+
 	intel_dp_link_training_set_mode(intel_dp,
-					crtc_state->port_clock, crtc_state->vrr.flipline);
+					crtc_state->port_clock, enable_msa_timing_par_ignore);
 }
 
 void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,