@@ -1108,14 +1108,9 @@ static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin ||
old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax ||
old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband ||
- old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full;
-}
-
-static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
- const struct intel_crtc_state *new_crtc_state)
-{
- return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
- old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
+ old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full ||
+ old_crtc_state->vrr.cmrr_m != new_crtc_state->vrr.cmrr_m ||
+ old_crtc_state->vrr.cmrr_n != new_crtc_state->vrr.cmrr_n;
}
static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state,
@@ -5760,9 +5755,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(vrr.guardband);
PIPE_CONF_CHECK_I(vrr.vsync_start);
PIPE_CONF_CHECK_I(vrr.vsync_end);
- PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
- PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
- PIPE_CONF_CHECK_BOOL(cmrr.enable);
+ PIPE_CONF_CHECK_LLI(vrr.cmrr_m);
+ PIPE_CONF_CHECK_LLI(vrr.cmrr_n);
}
#undef PIPE_CONF_CHECK_X
@@ -7183,8 +7177,7 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state,
intel_crtc_needs_fastset(new_crtc_state))
icl_set_pipe_chicken(new_crtc_state);
- if (vrr_params_changed(old_crtc_state, new_crtc_state) ||
- cmrr_params_changed(old_crtc_state, new_crtc_state))
+ if (vrr_params_changed(old_crtc_state, new_crtc_state))
intel_vrr_set_transcoder_timings(new_crtc_state);
}
@@ -1294,14 +1294,9 @@ struct intel_crtc_state {
u16 flipline, vmin, vmax, guardband;
u32 vsync_end, vsync_start;
enum intel_vrrtg_mode mode;
+ u64 cmrr_n, cmrr_m; /* Content Match Refresh Rate M and N */
} vrr;
- /* Content Match Refresh Rate state */
- struct {
- bool enable;
- u64 cmrr_n, cmrr_m;
- } cmrr;
-
/* Stream Splitter for eDP MSO */
struct {
bool enable;
@@ -2809,7 +2809,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
as_sdp->length = 0x9;
as_sdp->duration_incr_ms = 0;
- if (crtc_state->cmrr.enable) {
+ if (crtc_state->vrr.mode == INTEL_VRRTG_MODE_CMRR) {
as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
as_sdp->vtotal = adjusted_mode->vtotal;
as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
@@ -151,12 +151,12 @@ cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required)
multiplier_n = 1000;
}
- crtc_state->cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal,
- multiplier_n);
+ crtc_state->vrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal,
+ multiplier_n);
vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_n),
- crtc_state->cmrr.cmrr_n);
+ crtc_state->vrr.cmrr_n);
adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_m);
- crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n);
+ crtc_state->vrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->vrr.cmrr_n);
return vtotal;
}
@@ -165,7 +165,6 @@ static
void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
{
crtc_state->vrr.tg_enable = true;
- crtc_state->cmrr.enable = true;
crtc_state->vrr.mode = INTEL_VRRTG_MODE_CMRR;
/*
* TODO: Compute precise target refresh rate to determine
@@ -334,15 +333,15 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
return;
}
- if (crtc_state->cmrr.enable) {
+ if (crtc_state->vrr.mode == INTEL_VRRTG_MODE_CMRR) {
intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
- upper_32_bits(crtc_state->cmrr.cmrr_m));
+ upper_32_bits(crtc_state->vrr.cmrr_m));
intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
- lower_32_bits(crtc_state->cmrr.cmrr_m));
+ lower_32_bits(crtc_state->vrr.cmrr_m));
intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
- upper_32_bits(crtc_state->cmrr.cmrr_n));
+ upper_32_bits(crtc_state->vrr.cmrr_n));
intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
- lower_32_bits(crtc_state->cmrr.cmrr_n));
+ lower_32_bits(crtc_state->vrr.cmrr_n));
}
intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
@@ -395,7 +394,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
VRR_VSYNC_END(crtc_state->vrr.vsync_end) |
VRR_VSYNC_START(crtc_state->vrr.vsync_start));
- if (crtc_state->cmrr.enable) {
+ if (crtc_state->vrr.mode == INTEL_VRRTG_MODE_CMRR) {
intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE |
trans_vrr_ctl(crtc_state));
@@ -437,12 +436,11 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
crtc_state->vrr.tg_enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
if (HAS_CMRR(display) && trans_vrr_ctl & VRR_CTL_CMRR_ENABLE) {
- crtc_state->cmrr.enable = true;
crtc_state->vrr.mode = INTEL_VRRTG_MODE_CMRR;
- crtc_state->cmrr.cmrr_n =
+ crtc_state->vrr.cmrr_n =
intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
TRANS_CMRR_N_HI(display, cpu_transcoder));
- crtc_state->cmrr.cmrr_m =
+ crtc_state->vrr.cmrr_m =
intel_de_read64_2x32(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
TRANS_CMRR_M_HI(display, cpu_transcoder));
} else if (trans_vrr_ctl & VRR_CTL_VRR_ENABLE) {
Since cmrr is now as a mode of operation of VRR timing generator, move its elements in the vrr struct. Replace cmrr.enable with vrr.mode INTEL_VRRTG_MODE_CMRR and move cmrr_m and cmrr_n in vrr struct. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 19 +++++--------- .../drm/i915/display/intel_display_types.h | 7 +---- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_vrr.c | 26 +++++++++---------- 4 files changed, 20 insertions(+), 34 deletions(-)