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11 Nov 2024 04:33:16 -0800 X-CSE-ConnectionGUID: o4l5+U5VRh+BMnxTj0Fy7w== X-CSE-MsgGUID: dHD6uqLeSrKuOWKdnGPL5A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,145,1728975600"; d="scan'208";a="117823242" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by fmviesa001.fm.intel.com with ESMTP; 11 Nov 2024 04:33:14 -0800 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, Suraj Kandpal Subject: [PATCH 2/3] drm/i915/watermark: Modify latency programmed into PKG_C_LATENCY Date: Mon, 11 Nov 2024 18:02:58 +0530 Message-Id: <20241111123259.1072534-2-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241111123259.1072534-1-suraj.kandpal@intel.com> References: <20241111123259.1072534-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Increase the latency programmed into PKG_C_LATENCY latency to be a multiple of line time which is written into WM_LINETIME. --v2 -Fix commit subject line [Sai Teja] -Use individual DISPLAY_VER checks instead of range [Sai Teja] -Initialize max_linetime [Sai Teja] --v3 -take into account the scenario when adjusted_latency is 0 [Vinod] WA: 22020299601 Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/skl_watermark.c | 26 ++++++++++++++------ 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index a97e90ac643f..e061015a89b0 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -2848,9 +2848,11 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state, * Program PKG_C_LATENCY Added Wake Time = 0 */ static void -skl_program_dpkgc_latency(struct drm_i915_private *i915, bool enable_dpkgc) +skl_program_dpkgc_latency(struct drm_i915_private *i915, + bool enable_dpkgc, + u32 max_linetime) { - u32 max_latency = LNL_PKG_C_LATENCY_MASK; + u32 adjusted_latency = LNL_PKG_C_LATENCY_MASK; u32 clear = 0, val = 0; u32 added_wake_time = 0; @@ -2858,15 +2860,22 @@ skl_program_dpkgc_latency(struct drm_i915_private *i915, bool enable_dpkgc) return; if (enable_dpkgc) { - max_latency = skl_watermark_max_latency(i915, 1); - if (max_latency == 0) - max_latency = LNL_PKG_C_LATENCY_MASK; + adjusted_latency = skl_watermark_max_latency(i915, 1); + + /* Wa_22020299601 */ + if ((DISPLAY_VER(i915) == 20 || DISPLAY_VER(i915) == 30) && + adjusted_latency != 0) + adjusted_latency = max_linetime * + DIV_ROUND_UP(adjusted_latency, max_linetime); + else + adjusted_latency = LNL_PKG_C_LATENCY_MASK; + added_wake_time = DSB_EXE_TIME + i915->display.sagv.block_time_us; } clear |= LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK; - val |= REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, max_latency); + val |= REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, adjusted_latency); val |= REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK, added_wake_time); intel_uncore_rmw(&i915->uncore, LNL_PKG_C_LATENCY, clear, val); @@ -2879,6 +2888,7 @@ skl_compute_wm(struct intel_atomic_state *state) struct intel_crtc_state __maybe_unused *new_crtc_state; int ret, i; bool enable_dpkgc = false; + u32 max_linetime = 0; for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { ret = skl_build_pipe_wm(state, crtc); @@ -2908,9 +2918,11 @@ skl_compute_wm(struct intel_atomic_state *state) new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline) || !new_crtc_state->vrr.enable) enable_dpkgc = true; + + max_linetime = max(new_crtc_state->linetime, max_linetime); } - skl_program_dpkgc_latency(to_i915(state->base.dev), enable_dpkgc); + skl_program_dpkgc_latency(to_i915(state->base.dev), enable_dpkgc, max_linetime); skl_print_wm_changes(state);