| Message ID | 20241119104521.575377-7-arun.r.murthy@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Display Global Histogram | expand |
> -----Original Message----- > From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Arun R > Murthy > Sent: Tuesday, November 19, 2024 4:15 PM > To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; dri- > devel@lists.freedesktop.org > Cc: Murthy, Arun R <arun.r.murthy@intel.com> > Subject: [PATCH 6/8] drm/i915/histogram: histogram delay counter doesnt > reset > > The delay counter for histogram does not reset and as a result the histogram > bin never gets updated. Workaround would be to use save and restore > histogram register. > Wa: 14014889975 This should be above the Signed-off-by > > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> > --- > drivers/gpu/drm/i915/display/intel_histogram.c | 17 +++++++++++++++++ > .../gpu/drm/i915/display/intel_histogram_regs.h | 1 + > 2 files changed, 18 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c > b/drivers/gpu/drm/i915/display/intel_histogram.c > index cba65f4260cd..fdcc64677e96 100644 > --- a/drivers/gpu/drm/i915/display/intel_histogram.c > +++ b/drivers/gpu/drm/i915/display/intel_histogram.c > @@ -74,6 +74,11 @@ static void intel_histogram_handle_int_work(struct > work_struct *work) > struct intel_display *display = to_intel_display(intel_crtc); > char *histogram_event[] = {"HISTOGRAM=1", NULL}; > > + /* Wa: 14014889975 */ > + if (IS_DISPLAY_VER(display, 12, 13)) We have shifted to using is_display_verx100 so you can use that instead Also there is no display ver 13 just 12 and then 14 so maybe this should be just display_ver == 12 > + intel_de_rmw(display, DPST_CTL(intel_crtc->pipe), > + DPST_CTL_RESTORE, 0); > + > /* > * TODO: PSR to be exited while reading the Histogram data > * Set DPST_CTL Bin Reg function select to TC @@ -94,6 +99,12 @@ > static void intel_histogram_handle_int_work(struct work_struct *work) > "sending HISTOGRAM event failed\n"); > } > > + /* Wa: 14014889975 */ > + if (IS_DISPLAY_VER(display, 12, 13)) > + /* Write the value read from DPST_CTL to DPST_CTL.Interrupt > Delay Counter(bit 23:16) */ > + intel_de_write(display, DPST_CTL(intel_crtc->pipe), > intel_de_read(display, > + DPST_CTL(intel_crtc->pipe)) | > DPST_CTL_RESTORE); > + From the WA it seems we need to write 0 in the above Guardband Interrupt Delay Counter (bits 23:16) when servicing interrupts And only write value read from dpst_ctl when enabling dpst_config or doing an adjustment Regards, Suraj Kandpal > /* Enable histogram interrupt */ > intel_de_rmw(display, DPST_GUARD(intel_crtc->pipe), > DPST_GUARD_HIST_INT_EN, > DPST_GUARD_HIST_INT_EN); > @@ -240,6 +251,12 @@ int intel_histogram_set_iet_lut(struct intel_crtc > *intel_crtc, u32 *data) > return -EINVAL; > } > > + /* Wa: 14014889975 */ > + if (IS_DISPLAY_VER(display, 12, 13)) > + /* Write the value read from DPST_CTL to DPST_CTL.Interrupt > Delay Counter(bit 23:16) */ > + intel_de_write(display, DPST_CTL(intel_crtc->pipe), > intel_de_read(display, > + DPST_CTL(intel_crtc->pipe)) | > DPST_CTL_RESTORE); > + > /* > * Set DPST_CTL Bin Reg function select to IE > * Set DPST_CTL Bin Register Index to 0 diff --git > a/drivers/gpu/drm/i915/display/intel_histogram_regs.h > b/drivers/gpu/drm/i915/display/intel_histogram_regs.h > index 1252b4f339a6..e50b1448bd40 100644 > --- a/drivers/gpu/drm/i915/display/intel_histogram_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_histogram_regs.h > @@ -16,6 +16,7 @@ > #define DPST_CTL_RESTORE REG_BIT(28) > #define DPST_CTL_IE_MODI_TABLE_EN REG_BIT(27) > #define DPST_CTL_HIST_MODE REG_BIT(24) > +#define DPST_CTL_GUARDBAND_INTERRUPT_DELAY_CNT > REG_GENMASK(23, 16) > #define DPST_CTL_ENHANCEMENT_MODE_MASK > REG_GENMASK(14, 13) > #define DPST_CTL_EN_MULTIPLICATIVE > REG_FIELD_PREP(DPST_CTL_ENHANCEMENT_MODE_MASK, 2) > #define DPST_CTL_IE_TABLE_VALUE_FORMAT REG_BIT(15) > -- > 2.25.1
diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c b/drivers/gpu/drm/i915/display/intel_histogram.c index cba65f4260cd..fdcc64677e96 100644 --- a/drivers/gpu/drm/i915/display/intel_histogram.c +++ b/drivers/gpu/drm/i915/display/intel_histogram.c @@ -74,6 +74,11 @@ static void intel_histogram_handle_int_work(struct work_struct *work) struct intel_display *display = to_intel_display(intel_crtc); char *histogram_event[] = {"HISTOGRAM=1", NULL}; + /* Wa: 14014889975 */ + if (IS_DISPLAY_VER(display, 12, 13)) + intel_de_rmw(display, DPST_CTL(intel_crtc->pipe), + DPST_CTL_RESTORE, 0); + /* * TODO: PSR to be exited while reading the Histogram data * Set DPST_CTL Bin Reg function select to TC @@ -94,6 +99,12 @@ static void intel_histogram_handle_int_work(struct work_struct *work) "sending HISTOGRAM event failed\n"); } + /* Wa: 14014889975 */ + if (IS_DISPLAY_VER(display, 12, 13)) + /* Write the value read from DPST_CTL to DPST_CTL.Interrupt Delay Counter(bit 23:16) */ + intel_de_write(display, DPST_CTL(intel_crtc->pipe), intel_de_read(display, + DPST_CTL(intel_crtc->pipe)) | DPST_CTL_RESTORE); + /* Enable histogram interrupt */ intel_de_rmw(display, DPST_GUARD(intel_crtc->pipe), DPST_GUARD_HIST_INT_EN, DPST_GUARD_HIST_INT_EN); @@ -240,6 +251,12 @@ int intel_histogram_set_iet_lut(struct intel_crtc *intel_crtc, u32 *data) return -EINVAL; } + /* Wa: 14014889975 */ + if (IS_DISPLAY_VER(display, 12, 13)) + /* Write the value read from DPST_CTL to DPST_CTL.Interrupt Delay Counter(bit 23:16) */ + intel_de_write(display, DPST_CTL(intel_crtc->pipe), intel_de_read(display, + DPST_CTL(intel_crtc->pipe)) | DPST_CTL_RESTORE); + /* * Set DPST_CTL Bin Reg function select to IE * Set DPST_CTL Bin Register Index to 0 diff --git a/drivers/gpu/drm/i915/display/intel_histogram_regs.h b/drivers/gpu/drm/i915/display/intel_histogram_regs.h index 1252b4f339a6..e50b1448bd40 100644 --- a/drivers/gpu/drm/i915/display/intel_histogram_regs.h +++ b/drivers/gpu/drm/i915/display/intel_histogram_regs.h @@ -16,6 +16,7 @@ #define DPST_CTL_RESTORE REG_BIT(28) #define DPST_CTL_IE_MODI_TABLE_EN REG_BIT(27) #define DPST_CTL_HIST_MODE REG_BIT(24) +#define DPST_CTL_GUARDBAND_INTERRUPT_DELAY_CNT REG_GENMASK(23, 16) #define DPST_CTL_ENHANCEMENT_MODE_MASK REG_GENMASK(14, 13) #define DPST_CTL_EN_MULTIPLICATIVE REG_FIELD_PREP(DPST_CTL_ENHANCEMENT_MODE_MASK, 2) #define DPST_CTL_IE_TABLE_VALUE_FORMAT REG_BIT(15)
The delay counter for histogram does not reset and as a result the histogram bin never gets updated. Workaround would be to use save and restore histogram register. Wa: 14014889975 Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> --- drivers/gpu/drm/i915/display/intel_histogram.c | 17 +++++++++++++++++ .../gpu/drm/i915/display/intel_histogram_regs.h | 1 + 2 files changed, 18 insertions(+)