@@ -7653,6 +7653,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
intel_atomic_get_old_crtc_state(state, crtc);
struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
+ struct intel_display *display = to_intel_display(crtc);
if (!new_crtc_state->hw.active)
return;
@@ -7665,7 +7666,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
new_crtc_state->update_planes &&
!new_crtc_state->vrr.enable &&
!new_crtc_state->do_async_flip &&
- !new_crtc_state->has_psr &&
+ (DISPLAY_VER(display) >= 20 || !new_crtc_state->has_psr) &&
!new_crtc_state->scaler_state.scaler_users &&
!old_crtc_state->scaler_state.scaler_users &&
!intel_crtc_needs_modeset(new_crtc_state) &&
Now as we have correct PSR2_MAN_TRK_CTL handling in place we can allow DSB usage also when PSR is enabled for LunarLake onwards. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)