From patchwork Mon Jan 27 10:28:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 13951205 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 06CFDC02188 for ; Mon, 27 Jan 2025 10:29:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A238410E2F4; Mon, 27 Jan 2025 10:29:28 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="hwQP0V+P"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 943EE10E4FD; Mon, 27 Jan 2025 10:29:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1737973767; x=1769509767; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zeiDlzdCrPz2Ybt6+7mjVcXJ0iJe4lV42KmYpHueCMQ=; b=hwQP0V+PDCn9xB/LqSA89VEs3K4kUgscFvNOZD2D4d1irKYLvJCdSb5j oSgLrQM7eYywgRb0VNacCK+lXVFifRTFa9H1zME9W5nMhZQgIrtAMTG/6 kW3+fJNUV+CdTuEhbdZoogzutMhpqKgSLFc0WD4SPI5Lo7loOPu/0nJJS EN1DyRgyNinjh7cS4oDSkl5M4t+NWGN6ADApdAVuSpHbE2CtAckz9Y1/s 7wUAzsd59zU4A3tNazqJ+/hJoT9nJCLF6sbHQ+IINr7FR13oyzw6STga0 L12yiWqXTOffEgCNZauTXw3sQ8SWoBmRLemlpjG6+ILpt2UtpV27HI05F w==; X-CSE-ConnectionGUID: x4LsXvpvTbO+PNJx81CsCw== X-CSE-MsgGUID: VHUJ6f66QiuHgSkfO61Ylg== X-IronPort-AV: E=McAfee;i="6700,10204,11314"; a="38529885" X-IronPort-AV: E=Sophos;i="6.12,310,1728975600"; d="scan'208";a="38529885" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jan 2025 02:29:27 -0800 X-CSE-ConnectionGUID: bMAC2OlBT+qtD+liAceDhQ== X-CSE-MsgGUID: srskOhLuTKCll402xZQfbw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="108837932" Received: from mjarzebo-mobl1.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.244.95]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jan 2025 02:29:26 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: animesh.manna@intel.com, ville.syrjala@intel.com, =?utf-8?q?Jouni_H?= =?utf-8?q?=C3=B6gander?= Subject: [PATCH v6 11/12] drm/i915/display: Ensure we have "Frame Change" event in DSB commit Date: Mon, 27 Jan 2025 12:28:45 +0200 Message-ID: <20250127102846.1237560-12-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127102846.1237560-1-jouni.hogander@intel.com> References: <20250127102846.1237560-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We may have commit which doesn't have any non-arming plane register writes. In that case there aren't "Frame Change" event before DSB vblank evasion which hangs as PIPEDSL register is reading as 0 when PSR state is SRDENT(PSR1) or DEEP_SLEEP(PSR2). Handle this by ensuring "Frame Change" event at the begin of DSB commit if using PSR/PR. v2: use intel_psr_trigger_frame_change_event Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_display.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 5db2af86d0c8a..67041d76763fe 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7725,6 +7725,14 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, intel_crtc_planes_update_noarm(new_crtc_state->dsb_commit, state, crtc); + /* + * Ensure we have "Frame Change" event when PSR state is + * SRDENT(PSR1) or DEEP_SLEEP(PSR2). Otherwise DSB vblank + * evasion hangs as PIPEDSL is reading as 0. + */ + intel_psr_trigger_frame_change_event(state, new_crtc_state->dsb_commit, + crtc); + intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit); if (intel_crtc_needs_color_update(new_crtc_state))