From patchwork Tue Jan 28 15:54:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Govindapillai X-Patchwork-Id: 13952700 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9BFAC02190 for ; Tue, 28 Jan 2025 15:55:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5A1B410E6A3; Tue, 28 Jan 2025 15:55:04 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="k/vQ1lzb"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id EC6E910E696; Tue, 28 Jan 2025 15:55:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738079702; x=1769615702; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=M3VQ9FDIE+4TJYwf+qeYdLn1IFfobayXBqrDNrrxZhY=; b=k/vQ1lzbxXkceWv42J8nqHwdIEMjOxm3I/jrDR9RzhMOZTpc2fR+qTmI cXz+OBpPGsvywkFfUcjbntX4wZxi4n0hlLLhsAWfIpqrXCFOaF2ilHaIa aWu9IUCOq07N9//DcvsWQVDWcUzbjpqGk/1WIgjpky++KJH8N8CDEs8rE 6GNY1lvRYO8emUY0tJJHLciqTkE/Pu65Y72atrkP4iwMw7yDl4dypiLzF xrCjtBui0kF1jEXa76DUB8YPIggTgIQBhbx1hD/2z5cEG6XyWxeWT8wie PCN6YKvfc5qZaBcsYLqbFjHB7fm5Z3EwRNF2+WF80zY0qgacOnh1GWJr9 A==; X-CSE-ConnectionGUID: bRIZrGfYSWOzQjZEBNTQwg== X-CSE-MsgGUID: NUtaTdonQTykWetmqyuLhw== X-IronPort-AV: E=McAfee;i="6700,10204,11329"; a="49228116" X-IronPort-AV: E=Sophos;i="6.13,241,1732608000"; d="scan'208";a="49228116" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2025 07:55:01 -0800 X-CSE-ConnectionGUID: NO5kBiYuTZuIDQWekmcDfQ== X-CSE-MsgGUID: k1qa/6QUQ/K7fal2+Ky+Dw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="139635416" Received: from slindbla-desk.ger.corp.intel.com (HELO vgovind2-mobl3.intel.com) ([10.245.246.171]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2025 07:54:59 -0800 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, ville.syrjala@intel.com, santhosh.reddy.guddati@intel.com, jani.saarinen@intel.com Subject: [PATCH v5 7/7] drm/i915/xe3: disable FBC if PSR2 selective fetch is enabled Date: Tue, 28 Jan 2025 17:54:18 +0200 Message-ID: <20250128155418.305595-8-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250128155418.305595-1-vinod.govindapillai@intel.com> References: <20250128155418.305595-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" It is not recommended to have both FBC dirty rect and PSR2 selective fetch be enabled at the same time. If PSR2 selective fetch or panel replay is on, mark FBC as not possible. v2: fix the condition to disable FBC if PSR2 enabled (Jani) v3: use HAS_FBC_DIRTY_RECT() Bspec: 68881 Signed-off-by: Vinod Govindapillai --- drivers/gpu/drm/i915/display/intel_fbc.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 5fdbc7c4e67e..dd2a44d0ded1 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -1462,9 +1462,14 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, * Display 12+ is not supporting FBC with PSR2. * Recommendation is to keep this combination disabled * Bspec: 50422 HSD: 14010260002 + * + * In Xe3, PSR2 selective fetch and FBC dirty rect feature cannot + * coexist. So if PSR2 selective fetch is supported then mark that + * FBC is not supported. + * TODO: Need a logic to decide between PSR2 and FBC Dirty rect */ - if (IS_DISPLAY_VER(display, 12, 14) && crtc_state->has_sel_update && - !crtc_state->has_panel_replay) { + if ((IS_DISPLAY_VER(display, 12, 14) || HAS_FBC_DIRTY_RECT(display)) && + crtc_state->has_sel_update && !crtc_state->has_panel_replay) { plane_state->no_fbc_reason = "PSR2 enabled"; return 0; }