| Message ID | 20250130184518.22353-2-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/i915/vrr: Fix DSB+VRR usage for PTL+ | expand |
On 1/31/2025 12:15 AM, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Add a functiuon for emitting a DSB poll instruction. We'll allow s/functiuon/function > the caller to specify the poll parameters. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_dsb.c | 19 +++++++++++++++++++ > drivers/gpu/drm/i915/display/intel_dsb.h | 3 +++ > 2 files changed, 22 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c > index 2f2812c23972..b68ee125afae 100644 > --- a/drivers/gpu/drm/i915/display/intel_dsb.c > +++ b/drivers/gpu/drm/i915/display/intel_dsb.c > @@ -452,6 +452,25 @@ void intel_dsb_wait_scanline_out(struct intel_atomic_state *state, > start, end); > } > > +void intel_dsb_poll(struct intel_dsb *dsb, > + i915_reg_t reg, u32 mask, u32 val, > + int wait, int count) Perhaps `wait_us` to convey that value is in microseconds. In any case change LGTM. Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > +{ > + struct intel_crtc *crtc = dsb->crtc; > + enum pipe pipe = crtc->pipe; > + > + intel_dsb_reg_write(dsb, DSB_POLLMASK(pipe, dsb->id), mask); > + intel_dsb_reg_write(dsb, DSB_POLLFUNC(pipe, dsb->id), > + DSB_POLL_ENABLE | > + DSB_POLL_WAIT(wait) | DSB_POLL_COUNT(count)); > + > + intel_dsb_noop(dsb, 5); > + > + intel_dsb_emit(dsb, val, > + (DSB_OPCODE_POLL << DSB_OPCODE_SHIFT) | > + i915_mmio_reg_offset(reg)); > +} > + > static void intel_dsb_align_tail(struct intel_dsb *dsb) > { > u32 aligned_tail, tail; > diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h > index da6df07a3c83..4511d1a1a187 100644 > --- a/drivers/gpu/drm/i915/display/intel_dsb.h > +++ b/drivers/gpu/drm/i915/display/intel_dsb.h > @@ -54,6 +54,9 @@ void intel_dsb_wait_scanline_out(struct intel_atomic_state *state, > int lower, int upper); > void intel_dsb_vblank_evade(struct intel_atomic_state *state, > struct intel_dsb *dsb); > +void intel_dsb_poll(struct intel_dsb *dsb, > + i915_reg_t reg, u32 mask, u32 val, > + int wait, int count); > void intel_dsb_chain(struct intel_atomic_state *state, > struct intel_dsb *dsb, > struct intel_dsb *chained_dsb,
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 2f2812c23972..b68ee125afae 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -452,6 +452,25 @@ void intel_dsb_wait_scanline_out(struct intel_atomic_state *state, start, end); } +void intel_dsb_poll(struct intel_dsb *dsb, + i915_reg_t reg, u32 mask, u32 val, + int wait, int count) +{ + struct intel_crtc *crtc = dsb->crtc; + enum pipe pipe = crtc->pipe; + + intel_dsb_reg_write(dsb, DSB_POLLMASK(pipe, dsb->id), mask); + intel_dsb_reg_write(dsb, DSB_POLLFUNC(pipe, dsb->id), + DSB_POLL_ENABLE | + DSB_POLL_WAIT(wait) | DSB_POLL_COUNT(count)); + + intel_dsb_noop(dsb, 5); + + intel_dsb_emit(dsb, val, + (DSB_OPCODE_POLL << DSB_OPCODE_SHIFT) | + i915_mmio_reg_offset(reg)); +} + static void intel_dsb_align_tail(struct intel_dsb *dsb) { u32 aligned_tail, tail; diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h index da6df07a3c83..4511d1a1a187 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.h +++ b/drivers/gpu/drm/i915/display/intel_dsb.h @@ -54,6 +54,9 @@ void intel_dsb_wait_scanline_out(struct intel_atomic_state *state, int lower, int upper); void intel_dsb_vblank_evade(struct intel_atomic_state *state, struct intel_dsb *dsb); +void intel_dsb_poll(struct intel_dsb *dsb, + i915_reg_t reg, u32 mask, u32 val, + int wait, int count); void intel_dsb_chain(struct intel_atomic_state *state, struct intel_dsb *dsb, struct intel_dsb *chained_dsb,