| Message ID | 20250207223159.14132-9-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/i915/vrr: Fix DSB+VRR usage for PTL+ | expand |
On 2/8/2025 4:01 AM, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Decode the DSB error interrupts into human readable > form for easier debugging. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dsb.c | 15 ++++++++++++--- > 1 file changed, 12 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c > index aba57ddfbb92..db69b1c676f7 100644 > --- a/drivers/gpu/drm/i915/display/intel_dsb.c > +++ b/drivers/gpu/drm/i915/display/intel_dsb.c > @@ -860,7 +860,16 @@ void intel_dsb_irq_handler(struct intel_display *display, > } > > errors = tmp & dsb_error_int_status(display); > - if (errors) > - drm_err(display->drm, "[CRTC:%d:%s] DSB %d error interrupt: 0x%x\n", > - crtc->base.base.id, crtc->base.name, dsb_id, errors); > + if (errors & DSB_ATS_FAULT_INT_STATUS) > + drm_err(display->drm, "[CRTC:%d:%s] DSB %d ATS fault\n", > + crtc->base.base.id, crtc->base.name, dsb_id); > + if (errors & DSB_GTT_FAULT_INT_STATUS) > + drm_err(display->drm, "[CRTC:%d:%s] DSB %d GTT fault\n", > + crtc->base.base.id, crtc->base.name, dsb_id); > + if (errors & DSB_RSPTIMEOUT_INT_STATUS) > + drm_err(display->drm, "[CRTC:%d:%s] DSB %d response timeout\n", > + crtc->base.base.id, crtc->base.name, dsb_id); > + if (errors & DSB_POLL_ERR_INT_STATUS) > + drm_err(display->drm, "[CRTC:%d:%s] DSB %d poll error\n", > + crtc->base.base.id, crtc->base.name, dsb_id); > }
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index aba57ddfbb92..db69b1c676f7 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -860,7 +860,16 @@ void intel_dsb_irq_handler(struct intel_display *display, } errors = tmp & dsb_error_int_status(display); - if (errors) - drm_err(display->drm, "[CRTC:%d:%s] DSB %d error interrupt: 0x%x\n", - crtc->base.base.id, crtc->base.name, dsb_id, errors); + if (errors & DSB_ATS_FAULT_INT_STATUS) + drm_err(display->drm, "[CRTC:%d:%s] DSB %d ATS fault\n", + crtc->base.base.id, crtc->base.name, dsb_id); + if (errors & DSB_GTT_FAULT_INT_STATUS) + drm_err(display->drm, "[CRTC:%d:%s] DSB %d GTT fault\n", + crtc->base.base.id, crtc->base.name, dsb_id); + if (errors & DSB_RSPTIMEOUT_INT_STATUS) + drm_err(display->drm, "[CRTC:%d:%s] DSB %d response timeout\n", + crtc->base.base.id, crtc->base.name, dsb_id); + if (errors & DSB_POLL_ERR_INT_STATUS) + drm_err(display->drm, "[CRTC:%d:%s] DSB %d poll error\n", + crtc->base.base.id, crtc->base.name, dsb_id); }