| Message ID | 20250211172431.2631083-2-juhapekka.heikkila@gmail.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add writing of WAIT_ON_DEPTH_STALL_DONE_DISABLE for gen12 | expand |
On Tue, Feb 11, 2025 at 07:24:31PM +0200, Juha-Pekka Heikkila wrote: > Add writing of WAIT_ON_DEPTH_STALL_DONE_DISABLE for gen12. This > is performance optimization, writing this bit disables the wait. > > Bspec: 46132 > > Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12411 > Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ > drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++ > 2 files changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 6dba65e54cdb..7423fdd5dcaf 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -1010,6 +1010,9 @@ > #define XEHP_L3SCQREG7 MCR_REG(0xb188) > #define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3) > > +#define XEHP_WM_CHICKEN2 MCR_REG(0x5584) WM_CHICKEN2/3 have existed since BDW. WM_CHICKEN1 since snb. Looks like our already existing GEN9_WM_CHICKEN3 define is also misnamed, and it's also missing the MCR_REG() so wouldn't even work when used on platforms that need steering. > +#define WAIT_ON_DEPTH_STALL_DONE_DISABLE REG_BIT(5) > + > #define GEN11_GLBLINVL _MMIO(0xb404) > #define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5) > #define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index db04c3ee02e2..affee4d4cee2 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1640,6 +1640,11 @@ static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal) > wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); > wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS); > } > + > + if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 0), IP_VER(12, 70))) { > + wa_mcr_write_or(wal, XEHP_WM_CHICKEN2, > + WAIT_ON_DEPTH_STALL_DONE_DISABLE); > + } > } > > static void > -- > 2.45.2
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 6dba65e54cdb..7423fdd5dcaf 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1010,6 +1010,9 @@ #define XEHP_L3SCQREG7 MCR_REG(0xb188) #define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3) +#define XEHP_WM_CHICKEN2 MCR_REG(0x5584) +#define WAIT_ON_DEPTH_STALL_DONE_DISABLE REG_BIT(5) + #define GEN11_GLBLINVL _MMIO(0xb404) #define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5) #define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index db04c3ee02e2..affee4d4cee2 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1640,6 +1640,11 @@ static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal) wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS); } + + if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 0), IP_VER(12, 70))) { + wa_mcr_write_or(wal, XEHP_WM_CHICKEN2, + WAIT_ON_DEPTH_STALL_DONE_DISABLE); + } } static void
Add writing of WAIT_ON_DEPTH_STALL_DONE_DISABLE for gen12. This is performance optimization, writing this bit disables the wait. Bspec: 46132 Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12411 Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++ 2 files changed, 8 insertions(+)