| Message ID | 20250212075742.995022-2-jouni.hogander@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | PSR DSB support | expand |
> -----Original Message----- > From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Jouni > Högander > Sent: Wednesday, February 12, 2025 1:27 PM > To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org > Cc: Hogander, Jouni <jouni.hogander@intel.com> > Subject: [PATCH v7 01/13] drm/i915/psr: Use PSR2_MAN_TRK_CTL CFF bit > only to send full update > > We are preparing for a change where only frontbuffer flush will use single > full frame bit of a new register (SFF_CTL) available on LunarLake onwards. > > It shouldn't be necessary to have SFF bit set if CFF bit is set in > PSR2_MAN_TRK_CTL -> removing setting it on all platforms as there is not > reason to have it different on older platforms. > > v2: commit message improved > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com> LGTM. Reviewed-by: Animesh Manna <animesh.manna@intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index 861e50ceef85..64e03d19cad5 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -2395,7 +2395,6 @@ static void psr2_man_trk_ctl_calc(struct > intel_crtc_state *crtc_state, > val |= man_trk_ctl_partial_frame_bit_get(display); > > if (full_update) { > - val |= man_trk_ctl_single_full_frame_bit_get(display); > val |= man_trk_ctl_continuos_full_frame(display); > goto exit; > } > -- > 2.43.0
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 861e50ceef85..64e03d19cad5 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2395,7 +2395,6 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, val |= man_trk_ctl_partial_frame_bit_get(display); if (full_update) { - val |= man_trk_ctl_single_full_frame_bit_get(display); val |= man_trk_ctl_continuos_full_frame(display); goto exit; }
We are preparing for a change where only frontbuffer flush will use single full frame bit of a new register (SFF_CTL) available on LunarLake onwards. It shouldn't be necessary to have SFF bit set if CFF bit is set in PSR2_MAN_TRK_CTL -> removing setting it on all platforms as there is not reason to have it different on older platforms. v2: commit message improved Signed-off-by: Jouni Högander <jouni.hogander@intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 1 - 1 file changed, 1 deletion(-)