From patchwork Fri Feb 14 09:21:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jocelyn Falempe X-Patchwork-Id: 13974661 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 70000C021A7 for ; Fri, 14 Feb 2025 09:26:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E2B6110EC24; Fri, 14 Feb 2025 09:26:51 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=redhat.com header.i=@redhat.com header.b="DSDFBs2z"; dkim-atps=neutral Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by gabe.freedesktop.org (Postfix) with ESMTPS id 21B6C10EC24 for ; Fri, 14 Feb 2025 09:26:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1739525210; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dQqSycQ1fqWL/nN54ugVfzTbnTa0jcXchrx6dYh7YeY=; b=DSDFBs2zZB314jYbP5Aur8pzTijVu01u9g0lx1nQTEAU8S5GdC0Sm4W6dwLqiICxXsMwZQ Xhrkv8umCvq2VaNKlJ/144ZcwZj763oyf8rQIP4052W1DhHlYniZuIiheATUTNotXZd69P biBBAJcv0dt5TWSblTvAwYdotLGMlWQ= Received: from mx-prod-mc-02.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-237-iuOVWitCP-yaFnaCyf3yoQ-1; Fri, 14 Feb 2025 04:26:44 -0500 X-MC-Unique: iuOVWitCP-yaFnaCyf3yoQ-1 X-Mimecast-MFC-AGG-ID: iuOVWitCP-yaFnaCyf3yoQ_1739525203 Received: from mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.111]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-02.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 2A34319373D9; Fri, 14 Feb 2025 09:26:43 +0000 (UTC) Received: from hydra.redhat.com (unknown [10.45.225.79]) by mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 97B6F180034D; Fri, 14 Feb 2025 09:26:39 +0000 (UTC) From: Jocelyn Falempe To: Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , David Airlie , Simona Vetter , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Jocelyn Falempe Subject: [PATCH v5 5/8] drm/i915/display: Add drm_panic support Date: Fri, 14 Feb 2025 10:21:40 +0100 Message-ID: <20250214092608.2555218-6-jfalempe@redhat.com> In-Reply-To: <20250214092608.2555218-1-jfalempe@redhat.com> References: <20250214092608.2555218-1-jfalempe@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This adds drm_panic support for a wide range of Intel GPU. I've tested it only on 4 laptops, Haswell (with 128MB of eDRAM), Comet Lake, Alder Lake, and Lunar Lake. For hardware using DPT, it's not possible to disable tiling, as you will need to reconfigure the way the GPU is accessing the framebuffer. Signed-off-by: Jocelyn Falempe --- v4: * Add support for Xe driver. .../gpu/drm/i915/display/intel_atomic_plane.c | 79 ++++++++++++++++++- 1 file changed, 78 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index 8a49d87d9bd9c..c229c8618b5db 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -33,17 +33,21 @@ #include #include +#include #include #include +#include #include #include #include +#include #include "i915_drv.h" #include "i915_config.h" #include "i9xx_plane_regs.h" #include "intel_atomic_plane.h" +#include "intel_bo.h" #include "intel_cdclk.h" #include "intel_cursor.h" #include "intel_display_rps.h" @@ -51,6 +55,7 @@ #include "intel_display_types.h" #include "intel_fb.h" #include "intel_fb_pin.h" +#include "intel_fbdev.h" #include "skl_scaler.h" #include "skl_watermark.h" @@ -1203,14 +1208,86 @@ intel_cleanup_plane_fb(struct drm_plane *plane, intel_plane_unpin_fb(old_plane_state); } +/* Only used by drm_panic get_scanout_buffer() and panic_flush(), so it is + * protected by the drm panic spinlock + */ +static struct iosys_map panic_map; + +static void intel_panic_flush(struct drm_plane *plane) +{ + struct intel_plane_state *plane_state = to_intel_plane_state(plane->state); + struct drm_i915_private *dev_priv = to_i915(plane->dev); + struct drm_framebuffer *fb = plane_state->hw.fb; + struct intel_plane *iplane = to_intel_plane(plane); + + /* Force a cache flush, otherwise the new pixels won't show up */ + drm_clflush_virt_range(panic_map.vaddr, fb->height * fb->pitches[0]); + + /* Don't disable tiling if it's the fbdev framebuffer.*/ + if (to_intel_framebuffer(fb) == intel_fbdev_framebuffer(dev_priv->display.fbdev.fbdev)) + return; + + if (fb->modifier && iplane->disable_tiling) + iplane->disable_tiling(iplane); +} + +static int intel_get_scanout_buffer(struct drm_plane *plane, + struct drm_scanout_buffer *sb) +{ + struct intel_plane_state *plane_state; + struct drm_gem_object *obj; + struct drm_framebuffer *fb; + struct drm_i915_private *dev_priv = to_i915(plane->dev); + + if (!plane->state || !plane->state->fb || !plane->state->visible) + return -ENODEV; + + plane_state = to_intel_plane_state(plane->state); + fb = plane_state->hw.fb; + obj = intel_fb_bo(fb); + if (!obj) + return -ENODEV; + + iosys_map_clear(&panic_map); + if (to_intel_framebuffer(fb) == intel_fbdev_framebuffer(dev_priv->display.fbdev.fbdev)) { + intel_fbdev_get_map(dev_priv->display.fbdev.fbdev, &panic_map); + } else { + /* Can't disable tiling if DPT is in use */ + if (intel_fb_uses_dpt(fb)) + return -EOPNOTSUPP; + + intel_bo_panic_map(obj, &panic_map); + } + if (iosys_map_is_null(&panic_map)) + return -ENOMEM; + + sb->map[0] = panic_map; + sb->width = fb->width; + sb->height = fb->height; + sb->format = fb->format; + sb->pitch[0] = fb->pitches[0]; + + return 0; +} + static const struct drm_plane_helper_funcs intel_plane_helper_funcs = { .prepare_fb = intel_prepare_plane_fb, .cleanup_fb = intel_cleanup_plane_fb, }; +static const struct drm_plane_helper_funcs intel_primary_plane_helper_funcs = { + .prepare_fb = intel_prepare_plane_fb, + .cleanup_fb = intel_cleanup_plane_fb, + .get_scanout_buffer = intel_get_scanout_buffer, + .panic_flush = intel_panic_flush, +}; + void intel_plane_helper_add(struct intel_plane *plane) { - drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); + if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) + drm_plane_helper_add(&plane->base, &intel_primary_plane_helper_funcs); + else + drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); } void intel_plane_init_cursor_vblank_work(struct intel_plane_state *old_plane_state,