@@ -158,8 +158,6 @@ static void intel_crtc_disable_noatomic_complete(struct intel_crtc *crtc)
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_bw_state *bw_state =
to_intel_bw_state(i915->display.bw.obj.state);
- struct intel_dbuf_state *dbuf_state =
- to_intel_dbuf_state(i915->display.dbuf.obj.state);
struct intel_pmdemand_state *pmdemand_state =
to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
struct intel_crtc_state *crtc_state =
@@ -178,8 +176,7 @@ static void intel_crtc_disable_noatomic_complete(struct intel_crtc *crtc)
intel_display_power_put_all_in_set(display, &crtc->enabled_power_domains);
intel_cdclk_crtc_disable_noatomic(crtc);
-
- dbuf_state->active_pipes &= ~BIT(pipe);
+ skl_wm_crtc_disable_noatomic(crtc);
bw_state->data_rate[pipe] = 0;
bw_state->num_active_planes[pipe] = 0;
@@ -3845,6 +3845,19 @@ static void skl_wm_get_hw_state_and_sanitize(struct drm_i915_private *i915)
skl_dbuf_sanitize(i915);
}
+void skl_wm_crtc_disable_noatomic(struct intel_crtc *crtc)
+{
+ struct intel_display *display = to_intel_display(crtc);
+ struct intel_dbuf_state *dbuf_state =
+ to_intel_dbuf_state(display->dbuf.obj.state);
+ enum pipe pipe = crtc->pipe;
+
+ if (DISPLAY_VER(display) < 9)
+ return;
+
+ dbuf_state->active_pipes &= ~BIT(pipe);
+}
+
void intel_wm_state_verify(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
@@ -41,6 +41,8 @@ bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
void intel_wm_state_verify(struct intel_atomic_state *state,
struct intel_crtc *crtc);
+void skl_wm_crtc_disable_noatomic(struct intel_crtc *crtc);
+
void skl_watermark_ipc_init(struct drm_i915_private *i915);
void skl_watermark_ipc_update(struct drm_i915_private *i915);
bool skl_watermark_ipc_enabled(struct drm_i915_private *i915);