From patchwork Mon Feb 24 06:17:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13988131 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 29C00C021BF for ; Mon, 24 Feb 2025 13:44:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 071D210E514; Mon, 24 Feb 2025 13:42:17 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="a0j+evg6"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id DEA0010E13C; Mon, 24 Feb 2025 06:29:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1740378585; x=1771914585; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yMZQYKOctiyCsMD/2BUjTQbDNNX62NkLNLdFnnyQQmo=; b=a0j+evg623mFvTkZn72CtcWAWcc9XkW6b8tlzvAzJqkEWbZyJLSrhY2T vege3ZIEnHKhxpw//+eADJPeqRaBRd3R6CtNocKRAfJ7QzV3jE/EArbVu 5PFkHYKDbqM5HqYLdsvo4RLI6urEB++346PTv2547TscSExvzVTkeJUh3 A3sqjgKVusbAv4N8cN+uUBftEDYehn2I/cUQt3ki2RINa4b3LagLa+W2p mYFqSBpvkv67J2BaLFPYZH224qc8QJCasrLcyeGu5lXaLq1mb1QUG8zgz U1Yp6Smq2o4CM1tFvnrEnPt7nwq2VXRyimwR9fyyUY18jB9tqIlgj83g6 Q==; X-CSE-ConnectionGUID: VtpzuNHlQPq+AoxScua63w== X-CSE-MsgGUID: cYmDKBe4R1uRLejXMw/0qQ== X-IronPort-AV: E=McAfee;i="6700,10204,11354"; a="28719660" X-IronPort-AV: E=Sophos;i="6.13,309,1732608000"; d="scan'208";a="28719660" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Feb 2025 22:29:45 -0800 X-CSE-ConnectionGUID: 5KMRQXMYSu2fJzNE4D3rbA== X-CSE-MsgGUID: gtfgqy0AS1CYBtRQ7U5ldQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="120076537" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Feb 2025 22:29:45 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 08/20] drm/i915/display: Enable MSA Ignore Timing PAR only when in not fixed_rr mode Date: Mon, 24 Feb 2025 11:47:05 +0530 Message-ID: <20250224061717.1095226-9-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250224061717.1095226-1-ankit.k.nautiyal@intel.com> References: <20250224061717.1095226-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" MSA Ignore Timing PAR enable is set in the DP sink when we enable variable refresh rate. Currently for link training we depend on flipline to decide whether we want to ignore the msa timings. With fixed refresh rate we will still fill the flipline in all cases whether panel supports VRR or not. Change the condition for link training to ignore the msa timings if vrr.in_range. Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 3cc06c916017..549e4ebd9404 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -725,7 +725,7 @@ static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { intel_dp_link_training_set_mode(intel_dp, - crtc_state->port_clock, crtc_state->vrr.flipline); + crtc_state->port_clock, crtc_state->vrr.in_range); } void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,