| Message ID | 20250227034106.1638203-1-ankit.k.nautiyal@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/i915/watermark: Check bounds for scaler_users for dsc prefill latency | expand |
> -----Original Message----- > From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com> > Sent: 27 February 2025 09:11 > To: intel-gfx@lists.freedesktop.org > Cc: intel-xe@lists.freedesktop.org; jani.nikula@linux.intel.com; Golani, > Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>; Nautiyal, > Ankit K <ankit.k.nautiyal@intel.com> > Subject: [PATCH] drm/i915/watermark: Check bounds for scaler_users for > dsc prefill latency > > Currently, during the computation of global watermarks, the latency for each > scaler user is calculated to compute the DSC prefill latency. > At this point, the number of scaler users can exceed the number of > supported scalers, which is checked later in intel_atomic_setup_scalers(). > > This can cause issues when the number of scaler users exceeds the number > of supported scalers. > > While checking for DSC prefill, ensure that the number of scaler users does > not exceed the number of supported scalers. > > Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/4341 > Fixes: a9b14af999b0 ("drm/i915/dsc: Check if vblank is sufficient for dsc > prefill") > Cc: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> > Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > Cc: Jani Nikula <jani.nikula@linux.intel.com> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > --- > drivers/gpu/drm/i915/display/skl_watermark.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c > b/drivers/gpu/drm/i915/display/skl_watermark.c > index 10a1daad28eb..58b91981e400 100644 > --- a/drivers/gpu/drm/i915/display/skl_watermark.c > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c > @@ -2314,6 +2314,7 @@ cdclk_prefill_adjustment(const struct > intel_crtc_state *crtc_state) static int dsc_prefill_latency(const struct > intel_crtc_state *crtc_state) { > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > const struct intel_crtc_scaler_state *scaler_state = > &crtc_state->scaler_state; > int linetime = DIV_ROUND_UP(1000 * crtc_state- > >hw.adjusted_mode.htotal, > @@ -2323,7 +2324,9 @@ dsc_prefill_latency(const struct intel_crtc_state > *crtc_state) > crtc_state->output_format == > INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1; > u32 dsc_prefill_latency = 0; > > - if (!crtc_state->dsc.compression_enable || !num_scaler_users) > + if (!crtc_state->dsc.compression_enable || > + !num_scaler_users || > + num_scaler_users > crtc->num_scalers) Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> > return dsc_prefill_latency; > > dsc_prefill_latency = DIV_ROUND_UP(15 * linetime * > chroma_downscaling_factor, 10); > -- > 2.45.2
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 10a1daad28eb..58b91981e400 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -2314,6 +2314,7 @@ cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state) static int dsc_prefill_latency(const struct intel_crtc_state *crtc_state) { + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); const struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal, @@ -2323,7 +2324,9 @@ dsc_prefill_latency(const struct intel_crtc_state *crtc_state) crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1; u32 dsc_prefill_latency = 0; - if (!crtc_state->dsc.compression_enable || !num_scaler_users) + if (!crtc_state->dsc.compression_enable || + !num_scaler_users || + num_scaler_users > crtc->num_scalers) return dsc_prefill_latency; dsc_prefill_latency = DIV_ROUND_UP(15 * linetime * chroma_downscaling_factor, 10);
Currently, during the computation of global watermarks, the latency for each scaler user is calculated to compute the DSC prefill latency. At this point, the number of scaler users can exceed the number of supported scalers, which is checked later in intel_atomic_setup_scalers(). This can cause issues when the number of scaler users exceeds the number of supported scalers. While checking for DSC prefill, ensure that the number of scaler users does not exceed the number of supported scalers. Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/4341 Fixes: a9b14af999b0 ("drm/i915/dsc: Check if vblank is sufficient for dsc prefill") Cc: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> --- drivers/gpu/drm/i915/display/skl_watermark.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)