| Message ID | 20250330172616.718188-1-vinod.govindapillai@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [v3] drm/i915/display: implement wa_18038517565 | expand |
On Sun, 2025-03-30 at 20:26 +0300, Vinod Govindapillai wrote: > Disable FBC compressor clock gating before enabling FBC and > clear it after disabling FBC. > > v2: update the DG2 registers for this wa > > v3: use local variable and single line reg definition (Jani) > > Bspec: 74212, 72197, 69741, 65555 > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> > --- > drivers/gpu/drm/i915/display/intel_fbc.c | 22 ++++++++++++++++++++++ > drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ > 2 files changed, 28 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c > b/drivers/gpu/drm/i915/display/intel_fbc.c > index e89cee323d8b..ce5b1e3f1c20 100644 > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > @@ -520,6 +520,20 @@ static void ilk_fbc_activate(struct intel_fbc > *fbc) > DPFC_CTL_EN | g4x_dpfc_ctl(fbc)); > } > > +static void fbc_compressor_clkgate_disable_wa(struct intel_fbc *fbc, > + bool disable) > +{ > + struct intel_display *display = fbc->display; > + > + if (display->platform.dg2) > + intel_de_rmw(display, GEN9_CLKGATE_DIS_4, > DG2_DPFC_GATING_DIS, > + disable ? DG2_DPFC_GATING_DIS : 0); > + else if (DISPLAY_VER(display) >= 14) > + intel_de_rmw(display, MTL_PIPE_CLKGATE_DIS2(fbc- > >id), > + MTL_DPFC_GATING_DIS, > + disable ? MTL_DPFC_GATING_DIS : 0); > +} > + > static void ilk_fbc_deactivate(struct intel_fbc *fbc) > { > struct intel_display *display = fbc->display; > @@ -533,6 +547,10 @@ static void ilk_fbc_deactivate(struct intel_fbc > *fbc) > if (dpfc_ctl & DPFC_CTL_EN) { > dpfc_ctl &= ~DPFC_CTL_EN; > intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), > dpfc_ctl); > + > + /* wa_18038517565 Enable DPFC clock gating after FBC > disable */ > + if (display->platform.dg2 || DISPLAY_VER(display) >= > 14) > + fbc_compressor_clkgate_disable_wa(fbc, > false); > } > } > > @@ -922,6 +940,10 @@ static void intel_fbc_program_workarounds(struct > intel_fbc *fbc) > if (DISPLAY_VER(display) >= 11 && !display->platform.dg2) > intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), > 0, > DPFC_CHICKEN_FORCE_SLB_INVALIDATION); > + > + /* wa_18038517565 Disable DPFC clock gating before FBC > enable */ > + if (display->platform.dg2 || DISPLAY_VER(display) >= 14) > + fbc_compressor_clkgate_disable_wa(fbc, true); > } > > static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc) > diff --git a/drivers/gpu/drm/i915/i915_reg.h > b/drivers/gpu/drm/i915/i915_reg.h > index c5064eebe063..49beab8e324d 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1077,6 +1077,7 @@ > > #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C) > #define BXT_GMBUS_GATING_DIS (1 << 14) > +#define DG2_DPFC_GATING_DIS REG_BIT(31) > > #define GEN9_CLKGATE_DIS_5 _MMIO(0x46540) > #define DPCE_GATING_DIS REG_BIT(17) > @@ -4242,6 +4243,11 @@ enum skl_power_gate { > #define MTL_CLKGATE_DIS_TRANS(dev_priv, > trans) _MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A) > #define > MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS REG_BIT(7) > > +#define _MTL_PIPE_CLKGATE_DIS2_A 0x60114 > +#define _MTL_PIPE_CLKGATE_DIS2_B 0x61114 > +#define MTL_PIPE_CLKGATE_DIS2(pipe) _MMIO_PIPE(pipe, > _MTL_PIPE_CLKGATE_DIS2_A, _MTL_PIPE_CLKGATE_DIS2_B) > +#define MTL_DPFC_GATING_DIS REG_BIT(6) > + > #define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700) > #define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8) > #define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index e89cee323d8b..ce5b1e3f1c20 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -520,6 +520,20 @@ static void ilk_fbc_activate(struct intel_fbc *fbc) DPFC_CTL_EN | g4x_dpfc_ctl(fbc)); } +static void fbc_compressor_clkgate_disable_wa(struct intel_fbc *fbc, + bool disable) +{ + struct intel_display *display = fbc->display; + + if (display->platform.dg2) + intel_de_rmw(display, GEN9_CLKGATE_DIS_4, DG2_DPFC_GATING_DIS, + disable ? DG2_DPFC_GATING_DIS : 0); + else if (DISPLAY_VER(display) >= 14) + intel_de_rmw(display, MTL_PIPE_CLKGATE_DIS2(fbc->id), + MTL_DPFC_GATING_DIS, + disable ? MTL_DPFC_GATING_DIS : 0); +} + static void ilk_fbc_deactivate(struct intel_fbc *fbc) { struct intel_display *display = fbc->display; @@ -533,6 +547,10 @@ static void ilk_fbc_deactivate(struct intel_fbc *fbc) if (dpfc_ctl & DPFC_CTL_EN) { dpfc_ctl &= ~DPFC_CTL_EN; intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl); + + /* wa_18038517565 Enable DPFC clock gating after FBC disable */ + if (display->platform.dg2 || DISPLAY_VER(display) >= 14) + fbc_compressor_clkgate_disable_wa(fbc, false); } } @@ -922,6 +940,10 @@ static void intel_fbc_program_workarounds(struct intel_fbc *fbc) if (DISPLAY_VER(display) >= 11 && !display->platform.dg2) intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), 0, DPFC_CHICKEN_FORCE_SLB_INVALIDATION); + + /* wa_18038517565 Disable DPFC clock gating before FBC enable */ + if (display->platform.dg2 || DISPLAY_VER(display) >= 14) + fbc_compressor_clkgate_disable_wa(fbc, true); } static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c5064eebe063..49beab8e324d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1077,6 +1077,7 @@ #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C) #define BXT_GMBUS_GATING_DIS (1 << 14) +#define DG2_DPFC_GATING_DIS REG_BIT(31) #define GEN9_CLKGATE_DIS_5 _MMIO(0x46540) #define DPCE_GATING_DIS REG_BIT(17) @@ -4242,6 +4243,11 @@ enum skl_power_gate { #define MTL_CLKGATE_DIS_TRANS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A) #define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS REG_BIT(7) +#define _MTL_PIPE_CLKGATE_DIS2_A 0x60114 +#define _MTL_PIPE_CLKGATE_DIS2_B 0x61114 +#define MTL_PIPE_CLKGATE_DIS2(pipe) _MMIO_PIPE(pipe, _MTL_PIPE_CLKGATE_DIS2_A, _MTL_PIPE_CLKGATE_DIS2_B) +#define MTL_DPFC_GATING_DIS REG_BIT(6) + #define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700) #define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8) #define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4)
Disable FBC compressor clock gating before enabling FBC and clear it after disabling FBC. v2: update the DG2 registers for this wa v3: use local variable and single line reg definition (Jani) Bspec: 74212, 72197, 69741, 65555 Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> --- drivers/gpu/drm/i915/display/intel_fbc.c | 22 ++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ 2 files changed, 28 insertions(+)