| Message ID | 20250401205431.502423-1-khaled.almahallawy@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [v2] drm/i915/display: Add link rate and lane count to i915_display_info | expand |
On Tue, 01 Apr 2025, Khaled Almahallawy <khaled.almahallawy@intel.com> wrote: > Adding link rate and lane count information to i915_display_info makes it > easier and faster to access this data compared to checking kernel logs. > This is particularly beneficial for individuals who are not familiar with > i915 in the following scenarios: > > * Debugging DP tunnel bandwidth usage in the Thunderbolt driver. > * During USB4 certification, it is necessary to know the link rate used by > the monitor to prove that the DP tunnel can handle required rates. > * In PHY CTS, when the connector probes are not mounted correctly, > some display lanes may not appear in the DP Oscilloscope, leading to CTS > failures. > > This change provides validation teams with an easy way to identify and > troubleshoot issues. > > v2: separate seq_printf line (Jani) > > Cc: Imre Deak <imre.deak@intel.com> > Cc: Jani Nikula <jani.nikula@intel.com> > Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display_debugfs.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > index 4c784bb7e14b..44df22bd7a18 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > @@ -552,9 +552,11 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc) > seq_printf(m, "\tpipe__mode=" DRM_MODE_FMT "\n", > DRM_MODE_ARG(&crtc_state->hw.pipe_mode)); > > - seq_printf(m, "\tpipe src=" DRM_RECT_FMT ", dither=%s, bpp=%d\n", > + seq_printf(m, "\tpipe src=" DRM_RECT_FMT ", dither=%s, bpp=%d", > DRM_RECT_ARG(&crtc_state->pipe_src), > str_yes_no(crtc_state->dither), crtc_state->pipe_bpp); > + seq_printf(m, ", port_clock=%d, lane_count=%d\n", > + crtc_state->port_clock, crtc_state->lane_count); I did mean separate *output* line, not just source line. > > intel_scaler_info(m, crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 4c784bb7e14b..44df22bd7a18 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -552,9 +552,11 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc) seq_printf(m, "\tpipe__mode=" DRM_MODE_FMT "\n", DRM_MODE_ARG(&crtc_state->hw.pipe_mode)); - seq_printf(m, "\tpipe src=" DRM_RECT_FMT ", dither=%s, bpp=%d\n", + seq_printf(m, "\tpipe src=" DRM_RECT_FMT ", dither=%s, bpp=%d", DRM_RECT_ARG(&crtc_state->pipe_src), str_yes_no(crtc_state->dither), crtc_state->pipe_bpp); + seq_printf(m, ", port_clock=%d, lane_count=%d\n", + crtc_state->port_clock, crtc_state->lane_count); intel_scaler_info(m, crtc);
Adding link rate and lane count information to i915_display_info makes it easier and faster to access this data compared to checking kernel logs. This is particularly beneficial for individuals who are not familiar with i915 in the following scenarios: * Debugging DP tunnel bandwidth usage in the Thunderbolt driver. * During USB4 certification, it is necessary to know the link rate used by the monitor to prove that the DP tunnel can handle required rates. * In PHY CTS, when the connector probes are not mounted correctly, some display lanes may not appear in the DP Oscilloscope, leading to CTS failures. This change provides validation teams with an easy way to identify and troubleshoot issues. v2: separate seq_printf line (Jani) Cc: Imre Deak <imre.deak@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> --- drivers/gpu/drm/i915/display/intel_display_debugfs.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)