From patchwork Fri Apr 26 13:01:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13644770 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 70F84C4345F for ; Fri, 26 Apr 2024 13:04:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E11501123A6; Fri, 26 Apr 2024 13:04:19 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Pz21OpgA"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id AB89D112392; Fri, 26 Apr 2024 13:04:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714136655; x=1745672655; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TqEcDCBSZ5JAsFsAZv9Fs3f6yhDPdYrjQqbw2QYdFlw=; b=Pz21OpgA3L9slrsg1aSDl9QPOfFZ7xfxVG/t/ESQwjsunOgmOLqEkNvg EB68H9vAuoa0SLOYjs4+LK3lGMwbBaZMix2874uz0r4hgXdPOxYo6SM7q G928ffLX9YGSZQcq1XhxeF0yUy4mmuwnKb14QX5qBB3Jst7KbkXv77c8o AMif5GERpsuQq3xBmaNOlCE7oYstZW8IuHRrKlzNOg9hzMjuG1Inq9vjr x6TB2bFu5+Y0Cn8pwANiBTPe5K8oOOSQQi7k6mIGHUlTdzg9ukNdv6vZk Zup5Iuupb9sYTA4vWECFPpYpWCb0bEEThjzwVyPoUyhvFoL65pvF4aZDz Q==; X-CSE-ConnectionGUID: 6Gu/mqdiSFak9zMKw9o3aA== X-CSE-MsgGUID: 0CwzZgRHR7CDn1Ib+ArNCQ== X-IronPort-AV: E=McAfee;i="6600,9927,11056"; a="12804123" X-IronPort-AV: E=Sophos;i="6.07,232,1708416000"; d="scan'208";a="12804123" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2024 06:04:15 -0700 X-CSE-ConnectionGUID: GDfOXaY8Q/uyjc0DmtTDGw== X-CSE-MsgGUID: xcu6hFBiRxiSGf/ItihSRA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,232,1708416000"; d="scan'208";a="25405566" Received: from dgarbuz-mobl1.ger.corp.intel.com (HELO localhost) ([10.252.48.145]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2024 06:04:15 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@intel.com Subject: [PATCH 009/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_5_IVB Date: Fri, 26 Apr 2024 16:01:34 +0300 Message-Id: <27b88ebe4040ed4c5cff9e5a61e675adba9929da.1714136165.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_CRC_RES_5_IVB register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 919ff34a7bb1..8bef21f74010 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -368,7 +368,7 @@ static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(dev_priv, pipe)), intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(dev_priv, pipe)), intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(dev_priv, pipe)), - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe))); + intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(dev_priv, pipe))); } static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2544d2f0220c..6f85d5b23c2c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1654,7 +1654,7 @@ #define PIPE_CRC_RES_2_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_2_A_IVB) #define PIPE_CRC_RES_3_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_3_A_IVB) #define PIPE_CRC_RES_4_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_4_A_IVB) -#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_5_A_IVB) +#define PIPE_CRC_RES_5_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_5_A_IVB) #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A) #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A)