diff mbox series

[v2,2/6] drm/i915/gvt: use proper i915_reg_t for calc_index() parameters

Message ID 282b19c44d83c96b52c261cfc7218e7e54076cba.1717773890.git.jani.nikula@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: gvt register macro cleanups, unused macro removals | expand

Commit Message

Jani Nikula June 7, 2024, 3:25 p.m. UTC 
In order to be able to use the proper register macros instead of the
underscore prefixed ones, pass i915_reg_t for the calc_index()
parameters.

Side note: DSPSURF is really about planes, not pipes. Fixed stride
doesn't work for plane C for CHV (but that's okay for gvt). This doesn't
support planes beyond C either. But all that is unrelated to the change
at hand.

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.wang.linux@gmail.com>
Cc: intel-gvt-dev@lists.freedesktop.org
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/gvt/handlers.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

Comments

Zhi Wang June 10, 2024, 10:56 a.m. UTC | #1 
On Fri,  7 Jun 2024 18:25:36 +0300
Jani Nikula <jani.nikula@intel.com> wrote:

> In order to be able to use the proper register macros instead of the
> underscore prefixed ones, pass i915_reg_t for the calc_index()
> parameters.
> 
> Side note: DSPSURF is really about planes, not pipes. Fixed stride
> doesn't work for plane C for CHV (but that's okay for gvt). This
> doesn't support planes beyond C either. But all that is unrelated to
> the change at hand.
> 
> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> Cc: Zhi Wang <zhi.wang.linux@gmail.com>
> Cc: intel-gvt-dev@lists.freedesktop.org
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/handlers.c | 18 ++++++++++--------
>  1 file changed, 10 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c
> b/drivers/gpu/drm/i915/gvt/handlers.c index
> a2e9d24d646e..b005ab0104ee 100644 ---
> a/drivers/gpu/drm/i915/gvt/handlers.c +++
> b/drivers/gpu/drm/i915/gvt/handlers.c @@ -881,9 +881,11 @@ static int
> check_fdi_rx_train_status(struct intel_vgpu *vgpu, 
>  #define INVALID_INDEX (~0U)
>  
> -static unsigned int calc_index(unsigned int offset, unsigned int
> start,
> -			       unsigned int next, i915_reg_t _end)
> +static unsigned int calc_index(unsigned int offset, i915_reg_t
> _start,
> +			       i915_reg_t _next, i915_reg_t _end)
>  {
> +	u32 start = i915_mmio_reg_offset(_start);
> +	u32 next = i915_mmio_reg_offset(_next);
>  	u32 end = i915_mmio_reg_offset(_end);
>  	unsigned int range = next - start;
>  
> @@ -894,13 +896,13 @@ static unsigned int calc_index(unsigned int
> offset, unsigned int start, }
>  
>  #define FDI_RX_CTL_TO_PIPE(offset) \
> -	calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL,
> FDI_RX_CTL(PIPE_C))
> +	calc_index(offset, FDI_RX_CTL(PIPE_A), FDI_RX_CTL(PIPE_B),
> FDI_RX_CTL(PIPE_C)) 
>  #define FDI_TX_CTL_TO_PIPE(offset) \
> -	calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL,
> FDI_TX_CTL(PIPE_C))
> +	calc_index(offset, FDI_TX_CTL(PIPE_A), FDI_TX_CTL(PIPE_B),
> FDI_TX_CTL(PIPE_C)) 
>  #define FDI_RX_IMR_TO_PIPE(offset) \
> -	calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR,
> FDI_RX_IMR(PIPE_C))
> +	calc_index(offset, FDI_RX_IMR(PIPE_A), FDI_RX_IMR(PIPE_B),
> FDI_RX_IMR(PIPE_C)) 
>  static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu,
>  		unsigned int offset, void *p_data, unsigned int
> bytes) @@ -944,7 +946,7 @@ static int update_fdi_rx_iir_status(struct
> intel_vgpu *vgpu, }
>  
>  #define DP_TP_CTL_TO_PORT(offset) \
> -	calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B,
> DP_TP_CTL(PORT_E))
> +	calc_index(offset, DP_TP_CTL(PORT_A), DP_TP_CTL(PORT_B),
> DP_TP_CTL(PORT_E)) 
>  static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned
> int offset, void *p_data, unsigned int bytes)
> @@ -1008,7 +1010,7 @@ static int south_chicken2_mmio_write(struct
> intel_vgpu *vgpu, }
>  
>  #define DSPSURF_TO_PIPE(offset) \
> -	calc_index(offset, _DSPASURF, _DSPBSURF, DSPSURF(dev_priv,
> PIPE_C))
> +	calc_index(offset, DSPSURF(dev_priv, PIPE_A),
> DSPSURF(dev_priv, PIPE_B), DSPSURF(dev_priv, PIPE_C)) 
>  static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int
> offset, void *p_data, unsigned int bytes)
> @@ -1031,7 +1033,7 @@ static int pri_surf_mmio_write(struct
> intel_vgpu *vgpu, unsigned int offset, }
>  
>  #define SPRSURF_TO_PIPE(offset) \
> -	calc_index(offset, _SPRA_SURF, _SPRB_SURF, SPRSURF(PIPE_C))
> +	calc_index(offset, SPRSURF(PIPE_A), SPRSURF(PIPE_B),
> SPRSURF(PIPE_C)) 
>  static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int
> offset, void *p_data, unsigned int bytes)

Reviwed-by: Zhi Wang <zhiwang@kernel.org>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index a2e9d24d646e..b005ab0104ee 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -881,9 +881,11 @@  static int check_fdi_rx_train_status(struct intel_vgpu *vgpu,
 
 #define INVALID_INDEX (~0U)
 
-static unsigned int calc_index(unsigned int offset, unsigned int start,
-			       unsigned int next, i915_reg_t _end)
+static unsigned int calc_index(unsigned int offset, i915_reg_t _start,
+			       i915_reg_t _next, i915_reg_t _end)
 {
+	u32 start = i915_mmio_reg_offset(_start);
+	u32 next = i915_mmio_reg_offset(_next);
 	u32 end = i915_mmio_reg_offset(_end);
 	unsigned int range = next - start;
 
@@ -894,13 +896,13 @@  static unsigned int calc_index(unsigned int offset, unsigned int start,
 }
 
 #define FDI_RX_CTL_TO_PIPE(offset) \
-	calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, FDI_RX_CTL(PIPE_C))
+	calc_index(offset, FDI_RX_CTL(PIPE_A), FDI_RX_CTL(PIPE_B), FDI_RX_CTL(PIPE_C))
 
 #define FDI_TX_CTL_TO_PIPE(offset) \
-	calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, FDI_TX_CTL(PIPE_C))
+	calc_index(offset, FDI_TX_CTL(PIPE_A), FDI_TX_CTL(PIPE_B), FDI_TX_CTL(PIPE_C))
 
 #define FDI_RX_IMR_TO_PIPE(offset) \
-	calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, FDI_RX_IMR(PIPE_C))
+	calc_index(offset, FDI_RX_IMR(PIPE_A), FDI_RX_IMR(PIPE_B), FDI_RX_IMR(PIPE_C))
 
 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu,
 		unsigned int offset, void *p_data, unsigned int bytes)
@@ -944,7 +946,7 @@  static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu,
 }
 
 #define DP_TP_CTL_TO_PORT(offset) \
-	calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, DP_TP_CTL(PORT_E))
+	calc_index(offset, DP_TP_CTL(PORT_A), DP_TP_CTL(PORT_B), DP_TP_CTL(PORT_E))
 
 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 		void *p_data, unsigned int bytes)
@@ -1008,7 +1010,7 @@  static int south_chicken2_mmio_write(struct intel_vgpu *vgpu,
 }
 
 #define DSPSURF_TO_PIPE(offset) \
-	calc_index(offset, _DSPASURF, _DSPBSURF, DSPSURF(dev_priv, PIPE_C))
+	calc_index(offset, DSPSURF(dev_priv, PIPE_A), DSPSURF(dev_priv, PIPE_B), DSPSURF(dev_priv, PIPE_C))
 
 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 		void *p_data, unsigned int bytes)
@@ -1031,7 +1033,7 @@  static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 }
 
 #define SPRSURF_TO_PIPE(offset) \
-	calc_index(offset, _SPRA_SURF, _SPRB_SURF, SPRSURF(PIPE_C))
+	calc_index(offset, SPRSURF(PIPE_A), SPRSURF(PIPE_B), SPRSURF(PIPE_C))
 
 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 		void *p_data, unsigned int bytes)