[5/5] multiple ring buffer support, fix a irq enable logic for BSD

Commit Message

Zou, Nanhai April 2, 2010, 5:30 a.m. UTC

None

Patch

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5d09e16..0a68f65 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -67,6 +67,11 @@  void
 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
 {
 	if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
+		I915_WRITE(GTIIR, mask);
+		(void) I915_READ(GTIIR);
+		dev_priv->gt_irq_enable_reg |= mask;
+		I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
+		(void) I915_READ(GTIER);
 		dev_priv->gt_irq_mask_reg &= ~mask;
 		I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
 		(void) I915_READ(GTIMR);
@@ -77,9 +82,15 @@  void
 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
 {
 	if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
+		dev_priv->gt_irq_enable_reg &= ~mask;
+		I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
+		(void) I915_READ(GTIER);
 		dev_priv->gt_irq_mask_reg |= mask;
 		I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
 		(void) I915_READ(GTIMR);
+		I915_WRITE(GTIIR, mask);
+		(void) I915_READ(GTIIR);
+
 	}
 }
 
@@ -1284,7 +1295,7 @@  static int ironlake_irq_postinstall(struct drm_device *dev)
 	/* enable kind of interrupts always enabled */
 	u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
 			   DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
-	u32 render_mask = GT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
+	u32 render_mask = 0; /* enable nothing initially */
 	u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
 			   SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;