| Message ID | 3540e31869bbb68abd6cae88375d214d3aa1f5e5.1731347547.git.jani.nikula@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/i915: intel_display conversions, cleanups | expand |
On Mon, Nov 11, 2024 at 07:53:34PM +0200, Jani Nikula wrote: > Rename display_irqs_enabled to vlv_display_irqs_enabled, to emphasize > it's really only about VLV/CHV. Only access it when running on VLV/CHV. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > .../gpu/drm/i915/display/intel_display_core.h | 9 ++++++- > .../gpu/drm/i915/display/intel_display_irq.c | 26 ++++++------------- > .../gpu/drm/i915/display/intel_hotplug_irq.c | 6 ++++- > 3 files changed, 21 insertions(+), 20 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h > index 45b7c6900adc..5ad66df1a85e 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_core.h > +++ b/drivers/gpu/drm/i915/display/intel_display_core.h > @@ -453,7 +453,14 @@ struct intel_display { > } ips; > > struct { > - bool display_irqs_enabled; > + /* > + * Most platforms treat the display irq block as an always-on > + * power domain. vlv/chv can disable it at runtime and need > + * special care to avoid writing any of the display block > + * registers outside of the power domain. We defer setting up > + * the display irqs in this case to the runtime pm. > + */ > + bool vlv_display_irqs_enabled; > > /* For i915gm/i945gm vblank irq workaround */ > u8 vblank_enabled; > diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c > index d5458b0d976b..50c1ca062b80 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_irq.c > +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c > @@ -434,7 +434,8 @@ void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv, > > spin_lock(&dev_priv->irq_lock); > > - if (!dev_priv->display.irq.display_irqs_enabled) { > + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && > + !dev_priv->display.irq.vlv_display_irqs_enabled) { > spin_unlock(&dev_priv->irq_lock); > return; > } > @@ -1499,7 +1500,7 @@ static void _vlv_display_irq_reset(struct drm_i915_private *dev_priv) > > void vlv_display_irq_reset(struct drm_i915_private *dev_priv) > { > - if (dev_priv->display.irq.display_irqs_enabled) > + if (dev_priv->display.irq.vlv_display_irqs_enabled) > _vlv_display_irq_reset(dev_priv); > } > > @@ -1522,7 +1523,7 @@ void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) > u32 enable_mask; > enum pipe pipe; > > - if (!dev_priv->display.irq.display_irqs_enabled) > + if (!dev_priv->display.irq.vlv_display_irqs_enabled) > return; > > pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS; > @@ -1697,10 +1698,10 @@ void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) > { > lockdep_assert_held(&dev_priv->irq_lock); > > - if (dev_priv->display.irq.display_irqs_enabled) > + if (dev_priv->display.irq.vlv_display_irqs_enabled) > return; > > - dev_priv->display.irq.display_irqs_enabled = true; > + dev_priv->display.irq.vlv_display_irqs_enabled = true; > > if (intel_irqs_enabled(dev_priv)) { > _vlv_display_irq_reset(dev_priv); > @@ -1712,10 +1713,10 @@ void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) > { > lockdep_assert_held(&dev_priv->irq_lock); > > - if (!dev_priv->display.irq.display_irqs_enabled) > + if (!dev_priv->display.irq.vlv_display_irqs_enabled) > return; > > - dev_priv->display.irq.display_irqs_enabled = false; > + dev_priv->display.irq.vlv_display_irqs_enabled = false; > > if (intel_irqs_enabled(dev_priv)) > _vlv_display_irq_reset(dev_priv); > @@ -1911,17 +1912,6 @@ void intel_display_irq_init(struct drm_i915_private *i915) > { > i915->drm.vblank_disable_immediate = true; > > - /* > - * Most platforms treat the display irq block as an always-on power > - * domain. vlv/chv can disable it at runtime and need special care to > - * avoid writing any of the display block registers outside of the power > - * domain. We defer setting up the display irqs in this case to the > - * runtime pm. > - */ > - i915->display.irq.display_irqs_enabled = true; > - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > - i915->display.irq.display_irqs_enabled = false; > - > intel_hotplug_irq_init(i915); > > INIT_WORK(&i915->display.irq.vblank_dc_work, > diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c > index cb64c6f0ad1b..476ac88087e0 100644 > --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c > +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c > @@ -1457,7 +1457,11 @@ void intel_hpd_enable_detection(struct intel_encoder *encoder) > > void intel_hpd_irq_setup(struct drm_i915_private *i915) > { > - if (i915->display.irq.display_irqs_enabled && i915->display.funcs.hotplug) > + if ((IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) && I like the overal change, but it is not just a 'Rename' as the commit message tells if we are changing conditions. > + !i915->display.irq.vlv_display_irqs_enabled) > + return; > + > + if (i915->display.funcs.hotplug) > i915->display.funcs.hotplug->hpd_irq_setup(i915); > } > > -- > 2.39.5 >
On Thu, 14 Nov 2024, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote: > On Mon, Nov 11, 2024 at 07:53:34PM +0200, Jani Nikula wrote: >> Rename display_irqs_enabled to vlv_display_irqs_enabled, to emphasize >> it's really only about VLV/CHV. Only access it when running on VLV/CHV. >> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> >> --- >> .../gpu/drm/i915/display/intel_display_core.h | 9 ++++++- >> .../gpu/drm/i915/display/intel_display_irq.c | 26 ++++++------------- >> .../gpu/drm/i915/display/intel_hotplug_irq.c | 6 ++++- >> 3 files changed, 21 insertions(+), 20 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h >> index 45b7c6900adc..5ad66df1a85e 100644 >> --- a/drivers/gpu/drm/i915/display/intel_display_core.h >> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h >> @@ -453,7 +453,14 @@ struct intel_display { >> } ips; >> >> struct { >> - bool display_irqs_enabled; >> + /* >> + * Most platforms treat the display irq block as an always-on >> + * power domain. vlv/chv can disable it at runtime and need >> + * special care to avoid writing any of the display block >> + * registers outside of the power domain. We defer setting up >> + * the display irqs in this case to the runtime pm. >> + */ >> + bool vlv_display_irqs_enabled; >> >> /* For i915gm/i945gm vblank irq workaround */ >> u8 vblank_enabled; >> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c >> index d5458b0d976b..50c1ca062b80 100644 >> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c >> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c >> @@ -434,7 +434,8 @@ void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv, >> >> spin_lock(&dev_priv->irq_lock); >> >> - if (!dev_priv->display.irq.display_irqs_enabled) { >> + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && >> + !dev_priv->display.irq.vlv_display_irqs_enabled) { >> spin_unlock(&dev_priv->irq_lock); >> return; >> } >> @@ -1499,7 +1500,7 @@ static void _vlv_display_irq_reset(struct drm_i915_private *dev_priv) >> >> void vlv_display_irq_reset(struct drm_i915_private *dev_priv) >> { >> - if (dev_priv->display.irq.display_irqs_enabled) >> + if (dev_priv->display.irq.vlv_display_irqs_enabled) >> _vlv_display_irq_reset(dev_priv); >> } >> >> @@ -1522,7 +1523,7 @@ void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) >> u32 enable_mask; >> enum pipe pipe; >> >> - if (!dev_priv->display.irq.display_irqs_enabled) >> + if (!dev_priv->display.irq.vlv_display_irqs_enabled) >> return; >> >> pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS; >> @@ -1697,10 +1698,10 @@ void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) >> { >> lockdep_assert_held(&dev_priv->irq_lock); >> >> - if (dev_priv->display.irq.display_irqs_enabled) >> + if (dev_priv->display.irq.vlv_display_irqs_enabled) >> return; >> >> - dev_priv->display.irq.display_irqs_enabled = true; >> + dev_priv->display.irq.vlv_display_irqs_enabled = true; >> >> if (intel_irqs_enabled(dev_priv)) { >> _vlv_display_irq_reset(dev_priv); >> @@ -1712,10 +1713,10 @@ void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) >> { >> lockdep_assert_held(&dev_priv->irq_lock); >> >> - if (!dev_priv->display.irq.display_irqs_enabled) >> + if (!dev_priv->display.irq.vlv_display_irqs_enabled) >> return; >> >> - dev_priv->display.irq.display_irqs_enabled = false; >> + dev_priv->display.irq.vlv_display_irqs_enabled = false; >> >> if (intel_irqs_enabled(dev_priv)) >> _vlv_display_irq_reset(dev_priv); >> @@ -1911,17 +1912,6 @@ void intel_display_irq_init(struct drm_i915_private *i915) >> { >> i915->drm.vblank_disable_immediate = true; >> >> - /* >> - * Most platforms treat the display irq block as an always-on power >> - * domain. vlv/chv can disable it at runtime and need special care to >> - * avoid writing any of the display block registers outside of the power >> - * domain. We defer setting up the display irqs in this case to the >> - * runtime pm. >> - */ >> - i915->display.irq.display_irqs_enabled = true; >> - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) >> - i915->display.irq.display_irqs_enabled = false; >> - >> intel_hotplug_irq_init(i915); >> >> INIT_WORK(&i915->display.irq.vblank_dc_work, >> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c >> index cb64c6f0ad1b..476ac88087e0 100644 >> --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c >> +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c >> @@ -1457,7 +1457,11 @@ void intel_hpd_enable_detection(struct intel_encoder *encoder) >> >> void intel_hpd_irq_setup(struct drm_i915_private *i915) >> { >> - if (i915->display.irq.display_irqs_enabled && i915->display.funcs.hotplug) >> + if ((IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) && > > I like the overal change, but it is not just a 'Rename' as the commit message > tells if we are changing conditions. The commit message does say, "Only access it when running on VLV/CHV.", but yeah, I could rephrase it. BR, Jani. > >> + !i915->display.irq.vlv_display_irqs_enabled) >> + return; >> + >> + if (i915->display.funcs.hotplug) >> i915->display.funcs.hotplug->hpd_irq_setup(i915); >> } >> >> -- >> 2.39.5 >>
On Fri, Nov 15, 2024 at 03:15:15PM +0200, Jani Nikula wrote: > On Thu, 14 Nov 2024, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote: > > On Mon, Nov 11, 2024 at 07:53:34PM +0200, Jani Nikula wrote: > >> Rename display_irqs_enabled to vlv_display_irqs_enabled, to emphasize > >> it's really only about VLV/CHV. Only access it when running on VLV/CHV. > >> > >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> > >> --- > >> .../gpu/drm/i915/display/intel_display_core.h | 9 ++++++- > >> .../gpu/drm/i915/display/intel_display_irq.c | 26 ++++++------------- > >> .../gpu/drm/i915/display/intel_hotplug_irq.c | 6 ++++- > >> 3 files changed, 21 insertions(+), 20 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h > >> index 45b7c6900adc..5ad66df1a85e 100644 > >> --- a/drivers/gpu/drm/i915/display/intel_display_core.h > >> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h > >> @@ -453,7 +453,14 @@ struct intel_display { > >> } ips; > >> > >> struct { > >> - bool display_irqs_enabled; > >> + /* > >> + * Most platforms treat the display irq block as an always-on > >> + * power domain. vlv/chv can disable it at runtime and need > >> + * special care to avoid writing any of the display block > >> + * registers outside of the power domain. We defer setting up > >> + * the display irqs in this case to the runtime pm. > >> + */ > >> + bool vlv_display_irqs_enabled; > >> > >> /* For i915gm/i945gm vblank irq workaround */ > >> u8 vblank_enabled; > >> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c > >> index d5458b0d976b..50c1ca062b80 100644 > >> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c > >> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c > >> @@ -434,7 +434,8 @@ void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv, > >> > >> spin_lock(&dev_priv->irq_lock); > >> > >> - if (!dev_priv->display.irq.display_irqs_enabled) { > >> + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && > >> + !dev_priv->display.irq.vlv_display_irqs_enabled) { > >> spin_unlock(&dev_priv->irq_lock); > >> return; > >> } > >> @@ -1499,7 +1500,7 @@ static void _vlv_display_irq_reset(struct drm_i915_private *dev_priv) > >> > >> void vlv_display_irq_reset(struct drm_i915_private *dev_priv) > >> { > >> - if (dev_priv->display.irq.display_irqs_enabled) > >> + if (dev_priv->display.irq.vlv_display_irqs_enabled) > >> _vlv_display_irq_reset(dev_priv); > >> } > >> > >> @@ -1522,7 +1523,7 @@ void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) > >> u32 enable_mask; > >> enum pipe pipe; > >> > >> - if (!dev_priv->display.irq.display_irqs_enabled) > >> + if (!dev_priv->display.irq.vlv_display_irqs_enabled) > >> return; > >> > >> pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS; > >> @@ -1697,10 +1698,10 @@ void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) > >> { > >> lockdep_assert_held(&dev_priv->irq_lock); > >> > >> - if (dev_priv->display.irq.display_irqs_enabled) > >> + if (dev_priv->display.irq.vlv_display_irqs_enabled) > >> return; > >> > >> - dev_priv->display.irq.display_irqs_enabled = true; > >> + dev_priv->display.irq.vlv_display_irqs_enabled = true; > >> > >> if (intel_irqs_enabled(dev_priv)) { > >> _vlv_display_irq_reset(dev_priv); > >> @@ -1712,10 +1713,10 @@ void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) > >> { > >> lockdep_assert_held(&dev_priv->irq_lock); > >> > >> - if (!dev_priv->display.irq.display_irqs_enabled) > >> + if (!dev_priv->display.irq.vlv_display_irqs_enabled) > >> return; > >> > >> - dev_priv->display.irq.display_irqs_enabled = false; > >> + dev_priv->display.irq.vlv_display_irqs_enabled = false; > >> > >> if (intel_irqs_enabled(dev_priv)) > >> _vlv_display_irq_reset(dev_priv); > >> @@ -1911,17 +1912,6 @@ void intel_display_irq_init(struct drm_i915_private *i915) > >> { > >> i915->drm.vblank_disable_immediate = true; > >> > >> - /* > >> - * Most platforms treat the display irq block as an always-on power > >> - * domain. vlv/chv can disable it at runtime and need special care to > >> - * avoid writing any of the display block registers outside of the power > >> - * domain. We defer setting up the display irqs in this case to the > >> - * runtime pm. > >> - */ > >> - i915->display.irq.display_irqs_enabled = true; > >> - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > >> - i915->display.irq.display_irqs_enabled = false; > >> - > >> intel_hotplug_irq_init(i915); > >> > >> INIT_WORK(&i915->display.irq.vblank_dc_work, > >> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c > >> index cb64c6f0ad1b..476ac88087e0 100644 > >> --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c > >> +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c > >> @@ -1457,7 +1457,11 @@ void intel_hpd_enable_detection(struct intel_encoder *encoder) > >> > >> void intel_hpd_irq_setup(struct drm_i915_private *i915) > >> { > >> - if (i915->display.irq.display_irqs_enabled && i915->display.funcs.hotplug) > >> + if ((IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) && > > > > I like the overal change, but it is not just a 'Rename' as the commit message > > tells if we are changing conditions. > > The commit message does say, "Only access it when running on VLV/CHV.", > but yeah, I could rephrase it. looking again and everything really looks good. My only problem is with the word 'Rename' in the commit message... Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > BR, > Jani. > > > > > > >> + !i915->display.irq.vlv_display_irqs_enabled) > >> + return; > >> + > >> + if (i915->display.funcs.hotplug) > >> i915->display.funcs.hotplug->hpd_irq_setup(i915); > >> } > >> > >> -- > >> 2.39.5 > >> > > -- > Jani Nikula, Intel
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h index 45b7c6900adc..5ad66df1a85e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_core.h +++ b/drivers/gpu/drm/i915/display/intel_display_core.h @@ -453,7 +453,14 @@ struct intel_display { } ips; struct { - bool display_irqs_enabled; + /* + * Most platforms treat the display irq block as an always-on + * power domain. vlv/chv can disable it at runtime and need + * special care to avoid writing any of the display block + * registers outside of the power domain. We defer setting up + * the display irqs in this case to the runtime pm. + */ + bool vlv_display_irqs_enabled; /* For i915gm/i945gm vblank irq workaround */ u8 vblank_enabled; diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index d5458b0d976b..50c1ca062b80 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -434,7 +434,8 @@ void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv, spin_lock(&dev_priv->irq_lock); - if (!dev_priv->display.irq.display_irqs_enabled) { + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && + !dev_priv->display.irq.vlv_display_irqs_enabled) { spin_unlock(&dev_priv->irq_lock); return; } @@ -1499,7 +1500,7 @@ static void _vlv_display_irq_reset(struct drm_i915_private *dev_priv) void vlv_display_irq_reset(struct drm_i915_private *dev_priv) { - if (dev_priv->display.irq.display_irqs_enabled) + if (dev_priv->display.irq.vlv_display_irqs_enabled) _vlv_display_irq_reset(dev_priv); } @@ -1522,7 +1523,7 @@ void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) u32 enable_mask; enum pipe pipe; - if (!dev_priv->display.irq.display_irqs_enabled) + if (!dev_priv->display.irq.vlv_display_irqs_enabled) return; pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS; @@ -1697,10 +1698,10 @@ void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) { lockdep_assert_held(&dev_priv->irq_lock); - if (dev_priv->display.irq.display_irqs_enabled) + if (dev_priv->display.irq.vlv_display_irqs_enabled) return; - dev_priv->display.irq.display_irqs_enabled = true; + dev_priv->display.irq.vlv_display_irqs_enabled = true; if (intel_irqs_enabled(dev_priv)) { _vlv_display_irq_reset(dev_priv); @@ -1712,10 +1713,10 @@ void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) { lockdep_assert_held(&dev_priv->irq_lock); - if (!dev_priv->display.irq.display_irqs_enabled) + if (!dev_priv->display.irq.vlv_display_irqs_enabled) return; - dev_priv->display.irq.display_irqs_enabled = false; + dev_priv->display.irq.vlv_display_irqs_enabled = false; if (intel_irqs_enabled(dev_priv)) _vlv_display_irq_reset(dev_priv); @@ -1911,17 +1912,6 @@ void intel_display_irq_init(struct drm_i915_private *i915) { i915->drm.vblank_disable_immediate = true; - /* - * Most platforms treat the display irq block as an always-on power - * domain. vlv/chv can disable it at runtime and need special care to - * avoid writing any of the display block registers outside of the power - * domain. We defer setting up the display irqs in this case to the - * runtime pm. - */ - i915->display.irq.display_irqs_enabled = true; - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) - i915->display.irq.display_irqs_enabled = false; - intel_hotplug_irq_init(i915); INIT_WORK(&i915->display.irq.vblank_dc_work, diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c index cb64c6f0ad1b..476ac88087e0 100644 --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c @@ -1457,7 +1457,11 @@ void intel_hpd_enable_detection(struct intel_encoder *encoder) void intel_hpd_irq_setup(struct drm_i915_private *i915) { - if (i915->display.irq.display_irqs_enabled && i915->display.funcs.hotplug) + if ((IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) && + !i915->display.irq.vlv_display_irqs_enabled) + return; + + if (i915->display.funcs.hotplug) i915->display.funcs.hotplug->hpd_irq_setup(i915); }
Rename display_irqs_enabled to vlv_display_irqs_enabled, to emphasize it's really only about VLV/CHV. Only access it when running on VLV/CHV. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- .../gpu/drm/i915/display/intel_display_core.h | 9 ++++++- .../gpu/drm/i915/display/intel_display_irq.c | 26 ++++++------------- .../gpu/drm/i915/display/intel_hotplug_irq.c | 6 ++++- 3 files changed, 21 insertions(+), 20 deletions(-)