| Message ID | 3e2e12f6-a5bd-858f-7454-fce19f70cf30@redhat.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | i915 clear-residuals BYT + IVB rendering issue + possible fix | expand |
On Wed, May 12, 2021 at 12:06:23PM +0200, Hans de Goede wrote: > Hi All, > > We (Fedora) received a bug-report about rendering issues > on BYT and IVB caused by the i915 clear-residuals work > which landed in 5.10.y : > > The Fedora bug: > https://bugzilla.redhat.com/show_bug.cgi?id=1959581 > > Points to these i915 bugs: > https://gitlab.freedesktop.org/drm/intel/-/issues/3071 > https://gitlab.freedesktop.org/drm/intel/-/issues/3081#note_890606 > > With the second link containing a possible fix which looks promising > if someone can take a look at this, then that would be great: > > diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c > index de575fdb0..054a0f5b8 100644 > --- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c > +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c > @@ -397,7 +397,7 @@ static void emit_batch(struct i915_vma * const vma, > gen7_emit_pipeline_invalidate(&cmds); > batch_add(&cmds, MI_LOAD_REGISTER_IMM(2)); > batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0_GEN7)); > - batch_add(&cmds, 0xffff0000); > + batch_add(&cmds, 0xfffb0000); > batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_1)); > batch_add(&cmds, 0xffff0000 | PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); > gen7_emit_pipeline_invalidate(&cmds); > > Note the: > https://gitlab.freedesktop.org/drm/intel/-/issues/3081#note_890606 > > Link contains details about the what and why of this change. There's a patch on the list already https://patchwork.freedesktop.org/patch/431109/?series=89502&rev=1 I suppose it needs a s/IVB_GT1/IVB/ to be consistent with the current w/a setup. Other than that it seems correct. But I still don't understand how it fixes rendering corruption.
Hi, On 5/12/21 2:18 PM, Ville Syrjälä wrote: > On Wed, May 12, 2021 at 12:06:23PM +0200, Hans de Goede wrote: >> Hi All, >> >> We (Fedora) received a bug-report about rendering issues >> on BYT and IVB caused by the i915 clear-residuals work >> which landed in 5.10.y : >> >> The Fedora bug: >> https://bugzilla.redhat.com/show_bug.cgi?id=1959581 >> >> Points to these i915 bugs: >> https://gitlab.freedesktop.org/drm/intel/-/issues/3071 >> https://gitlab.freedesktop.org/drm/intel/-/issues/3081#note_890606 >> >> With the second link containing a possible fix which looks promising >> if someone can take a look at this, then that would be great: >> >> diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c >> index de575fdb0..054a0f5b8 100644 >> --- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c >> +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c >> @@ -397,7 +397,7 @@ static void emit_batch(struct i915_vma * const vma, >> gen7_emit_pipeline_invalidate(&cmds); >> batch_add(&cmds, MI_LOAD_REGISTER_IMM(2)); >> batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0_GEN7)); >> - batch_add(&cmds, 0xffff0000); >> + batch_add(&cmds, 0xfffb0000); >> batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_1)); >> batch_add(&cmds, 0xffff0000 | PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); >> gen7_emit_pipeline_invalidate(&cmds); >> >> Note the: >> https://gitlab.freedesktop.org/drm/intel/-/issues/3081#note_890606 >> >> Link contains details about the what and why of this change. > > There's a patch on the list already > https://patchwork.freedesktop.org/patch/431109/?series=89502&rev=1 So that was posted 2 weeks ago; and we (Fedora) have had several bug reports about firefox rendering corruption on BYT + IVB machines, ever since the i915 clear-residuals changes landed in 5.10.y, I took action on this last one since now their seems to be a clear fix. > I suppose it needs a s/IVB_GT1/IVB/ to be consistent with the current > w/a setup. Other than that it seems correct. > > But I still don't understand how it fixes rendering corruption. You mean the remark about how the change should not impact other rendering contexts? I guess it may be global, rcs_engine_wa_init() which does not sound like it is a per context function, but I could very well be wrong, has this: if (IS_IVYBRIDGE(i915)) { /* WaDisableEarlyCull:ivb */ wa_masked_en(wal, _3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); if (0) { /* causes HiZ corruption on ivb:gt1 */ /* enable HiZ Raw Stall Optimization */ wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); } ... Notice how the comment explictly says that disabling the HIZ_RAW_STALL_OPT_DISABLE (thus enabling the opt) is known to cause HiZ corruption, so that at least explains why this bit matters. Maybe the bug is such that triggering it from with the clear-residuals context also impacts other contexts? And as I already said this is a regression which has been biting Fedora users for a while now and the fix obviously seems correct given the above comment which I quoted, so can we please get this merged ? Regards, Hans
diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c index de575fdb0..054a0f5b8 100644 --- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c @@ -397,7 +397,7 @@ static void emit_batch(struct i915_vma * const vma, gen7_emit_pipeline_invalidate(&cmds); batch_add(&cmds, MI_LOAD_REGISTER_IMM(2)); batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0_GEN7)); - batch_add(&cmds, 0xffff0000); + batch_add(&cmds, 0xfffb0000); batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_1)); batch_add(&cmds, 0xffff0000 | PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); gen7_emit_pipeline_invalidate(&cmds);