| Message ID | 3f7aae89cf63760bca43b54102c76b3ed2cf8735.1714399071.git.jani.nikula@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/color: first batch of implicit dev_priv removals | expand |
On Mon, Apr 29, 2024 at 05:02:18PM +0300, Jani Nikula wrote: > Avoid the implicit dev_priv local variable use, and pass dev_priv > explicitly to the PIPE_WGC_C11_C10 register macro. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/display/intel_color.c | 4 ++-- > drivers/gpu/drm/i915/display/intel_color_regs.h | 2 +- > 2 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c > index f96d6af028b6..11b5891a8399 100644 > --- a/drivers/gpu/drm/i915/display/intel_color.c > +++ b/drivers/gpu/drm/i915/display/intel_color.c > @@ -621,7 +621,7 @@ static void vlv_load_wgc_csc(struct intel_crtc *crtc, > intel_de_write_fw(dev_priv, PIPE_WGC_C02(dev_priv, pipe), > csc->coeff[2]); > > - intel_de_write_fw(dev_priv, PIPE_WGC_C11_C10(pipe), > + intel_de_write_fw(dev_priv, PIPE_WGC_C11_C10(dev_priv, pipe), > csc->coeff[4] << 16 | csc->coeff[3]); > intel_de_write_fw(dev_priv, PIPE_WGC_C12(pipe), > csc->coeff[5]); > @@ -646,7 +646,7 @@ static void vlv_read_wgc_csc(struct intel_crtc *crtc, > tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C02(dev_priv, pipe)); > csc->coeff[2] = tmp & 0xffff; > > - tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C11_C10(pipe)); > + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C11_C10(dev_priv, pipe)); > csc->coeff[3] = tmp & 0xffff; > csc->coeff[4] = tmp >> 16; > > diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h b/drivers/gpu/drm/i915/display/intel_color_regs.h > index 741c0b8592d9..19b0255e0831 100644 > --- a/drivers/gpu/drm/i915/display/intel_color_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_color_regs.h > @@ -258,7 +258,7 @@ > > #define PIPE_WGC_C01_C00(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C01_C00) > #define PIPE_WGC_C02(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C02) > -#define PIPE_WGC_C11_C10(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C11_C10) > +#define PIPE_WGC_C11_C10(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C11_C10) > #define PIPE_WGC_C12(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C12) > #define PIPE_WGC_C21_C20(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C21_C20) > #define PIPE_WGC_C22(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C22) > -- > 2.39.2 >
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index f96d6af028b6..11b5891a8399 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -621,7 +621,7 @@ static void vlv_load_wgc_csc(struct intel_crtc *crtc, intel_de_write_fw(dev_priv, PIPE_WGC_C02(dev_priv, pipe), csc->coeff[2]); - intel_de_write_fw(dev_priv, PIPE_WGC_C11_C10(pipe), + intel_de_write_fw(dev_priv, PIPE_WGC_C11_C10(dev_priv, pipe), csc->coeff[4] << 16 | csc->coeff[3]); intel_de_write_fw(dev_priv, PIPE_WGC_C12(pipe), csc->coeff[5]); @@ -646,7 +646,7 @@ static void vlv_read_wgc_csc(struct intel_crtc *crtc, tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C02(dev_priv, pipe)); csc->coeff[2] = tmp & 0xffff; - tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C11_C10(pipe)); + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C11_C10(dev_priv, pipe)); csc->coeff[3] = tmp & 0xffff; csc->coeff[4] = tmp >> 16; diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h b/drivers/gpu/drm/i915/display/intel_color_regs.h index 741c0b8592d9..19b0255e0831 100644 --- a/drivers/gpu/drm/i915/display/intel_color_regs.h +++ b/drivers/gpu/drm/i915/display/intel_color_regs.h @@ -258,7 +258,7 @@ #define PIPE_WGC_C01_C00(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C01_C00) #define PIPE_WGC_C02(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C02) -#define PIPE_WGC_C11_C10(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C11_C10) +#define PIPE_WGC_C11_C10(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C11_C10) #define PIPE_WGC_C12(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C12) #define PIPE_WGC_C21_C20(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C21_C20) #define PIPE_WGC_C22(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C22)
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_WGC_C11_C10 register macro. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_color.c | 4 ++-- drivers/gpu/drm/i915/display/intel_color_regs.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-)