From patchwork Wed Jul 10 17:00:46 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Bell, Bryan J" X-Patchwork-Id: 2825833 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 073BBC0AB2 for ; Wed, 10 Jul 2013 17:01:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A9EDA20169 for ; Wed, 10 Jul 2013 17:01:25 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 5A8CF20165 for ; Wed, 10 Jul 2013 17:01:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 66AA4E63F5 for ; Wed, 10 Jul 2013 10:01:24 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 1D033E5BF4 for ; Wed, 10 Jul 2013 10:01:11 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP; 10 Jul 2013 10:02:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="4.87,1037,1363158000"; d="scan'208"; a="363232157" Received: from fmsmsx104.amr.corp.intel.com ([10.19.9.35]) by fmsmga001.fm.intel.com with ESMTP; 10 Jul 2013 10:01:51 -0700 Received: from fmsmsx113.amr.corp.intel.com (10.18.116.7) by FMSMSX104.amr.corp.intel.com (10.19.9.35) with Microsoft SMTP Server (TLS) id 14.3.123.3; Wed, 10 Jul 2013 10:00:47 -0700 Received: from fmsmsx107.amr.corp.intel.com ([169.254.9.172]) by FMSMSX113.amr.corp.intel.com ([169.254.4.208]) with mapi id 14.03.0123.003; Wed, 10 Jul 2013 10:00:48 -0700 From: "Bell, Bryan J" To: Ben Widawsky , Intel GFX Thread-Topic: [PATCH] drm/i915: Expose LLC size to user space Thread-Index: AQHOfRjqxECJ7TMVokSj8L+tE856ZpleIg2Q Date: Wed, 10 Jul 2013 17:00:46 +0000 Message-ID: <45EA1CA55A8B924B8A73C0520E7232CB62F8F52A@FMSMSX107.amr.corp.intel.com> References: <1373425083-1276-1-git-send-email-ben@bwidawsk.net> In-Reply-To: <1373425083-1276-1-git-send-email-ben@bwidawsk.net> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.1.200.108] MIME-Version: 1.0 Subject: Re: [Intel-gfx] [PATCH] drm/i915: Expose LLC size to user space X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Looks good, Can you update the comment? The pdf "Intel Processor Identification and the CPUID Instruction" is no longer available and the description of the CPUID instruction is now in the "Intel 64 and IA32 Architectures Developer's Manual: Vol. 2A -> section 3.2 -> CPUID" -----Original Message----- From: Ben Widawsky [mailto:ben@bwidawsk.net] Sent: Tuesday, July 09, 2013 7:58 PM To: Intel GFX Cc: Ben Widawsky; Chad Versace; Bell, Bryan J Subject: [PATCH] drm/i915: Expose LLC size to user space The algorithm/information was originally written by Chad, though I changed the control flow, and I think his original code had a couple of bugs, though I didn't look very hard before rewriting. That could have also been different interpretations of the spec. The excellent comments remain entirely copied from Chad's code. I've tested this on two platforms, and it seems to perform how I want. CC: Chad Versace CC: Bryan Bell Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_dma.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_gem.c | 53 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 56 insertions(+), 1 deletion(-) + dev_priv->llc_size = get_llc_size(dev); + /* Initialize fence registers to zero */ INIT_LIST_HEAD(&dev_priv->mm.fence_list); i915_gem_restore_fences(dev); -- 1.8.3.2 diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 0e22142..377949e 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -974,7 +974,7 @@ static int i915_getparam(struct drm_device *dev, void *data, value = 1; break; case I915_PARAM_HAS_LLC: - value = HAS_LLC(dev); + value = dev_priv->llc_size; break; case I915_PARAM_HAS_ALIASING_PPGTT: value = dev_priv->mm.aliasing_ppgtt ? 1 : 0; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index c8d6104..43a549d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1187,6 +1187,8 @@ typedef struct drm_i915_private { /* Old dri1 support infrastructure, beware the dragons ya fools entering * here! */ struct i915_dri1_state dri1; + + size_t llc_size; } drm_i915_private_t; /* Iterate over initialised rings */ diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index af61be8..a070686 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4282,6 +4282,57 @@ i915_gem_lastclose(struct drm_device *dev) DRM_ERROR("failed to idle hardware: %d\n", ret); } +/** + * Return the size, in bytes, of the CPU L3 cache size. If the CPU has +no L3 + * cache, or if an error occurs in obtaining the cache size, then return 0. + * From "Intel Processor Identification and the CPUID Instruction > +5.15 + * Deterministic Cache Parmaeters (Function 04h)": + * When EAX is initialized to a value of 4, the CPUID instruction returns + * deterministic cache information in the EAX, EBX, ECX and EDX registers. + * This function requires ECX be initialized with an index which indicates + * which cache to return information about. The OS is expected to call this + * function (CPUID.4) with ECX = 0, 1, 2, until EAX[4:0] == 0, indicating no + * more caches. The order in which the caches are returned is not specified + * and may change at Intel's discretion. + * + * Equation 5-4. Calculating the Cache Size in bytes: + * = (Ways +1) (Partitions +1) (Line Size +1) (Sets +1) + * = (EBX[31:22] +1) (EBX[21:12] +1) (EBX[11:0] +1 (ECX + 1) + */ +static size_t get_llc_size(struct drm_device *dev) { + u8 cnt = 0; + unsigned int eax, ebx, ecx, edx; + + if (!HAS_LLC(dev)) + return 0; + + do { + uint32_t cache_level; + uint32_t associativity, line_partitions, line_size, sets; + + eax = 4; + ecx = cnt; + __cpuid(&eax, &ebx, &ecx, &edx); + + cache_level = (eax >> 5) & 0x7; + if (cache_level != 3) + continue; + + associativity = ((ebx >> 22) & 0x3ff) + 1; + line_partitions = ((ebx >> 12) & 0x3ff) + 1; + line_size = (ebx & 0xfff) + 1; + sets = ecx + 1; + + return associativity * line_partitions * line_size * sets; + } while (eax & 0x1f && ++cnt); + + /* Let user space know we have LLC, but we can't figure it out */ + DRM_DEBUG_DRIVER("Couldn't find LLC size. Bug?\n"); + return 1; +} + + static void init_ring_lists(struct intel_ring_buffer *ring) { @@ -4333,6 +4384,8 @@ i915_gem_load(struct drm_device *dev) else dev_priv->num_fence_regs = 8;