Message ID | 4AA9EF66.4030501@ens-lyon.org (mailing list archive) |
---|---|
State | Accepted |
Headers | show |
On Fri, 2009-09-11 at 08:34 +0200, Brice Goglin wrote: > Eric Anholt wrote: > > The chipset flush was on the right track -- hitting the right amount of > > memory, and it appears to be the only way to flush on these chipsets, but the > > flush page was mapped uncached. As a result, the writes trying to clear the > > writeback cache ended up bypassing the cache, and not flushing anything! The > > wbinvd would flush out other writeback data and often cause the data we wanted > > to get flushed, but not always. By removing the setting of the page to UC > > and instead just clflushing the data we write to try to flush it, we get the > > desired behavior with no wbinvd. > > > > This helps a lot, thanks Eric. I've been running various things under > metacity and compiz during the last 10mn without problems while X would > usually hang after 10s. But I needed the below patch to build the > intel-agp driver as a module. Thanks!
Index: linux-2.6.31/arch/x86/mm/pageattr.c =================================================================== --- linux-2.6.31.orig/arch/x86/mm/pageattr.c 2009-09-11 08:02:14.000000000 +0200 +++ linux-2.6.31/arch/x86/mm/pageattr.c 2009-09-11 08:02:48.000000000 +0200 @@ -143,6 +143,7 @@ mb(); } +EXPORT_SYMBOL_GPL(clflush_cache_range); static void __cpa_flush_all(void *arg) {