From patchwork Mon Jun 2 10:34:59 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Richter X-Patchwork-Id: 4281131 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 065609F1D6 for ; Mon, 2 Jun 2014 10:35:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1DADD2026F for ; Mon, 2 Jun 2014 10:35:14 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 6882F20263 for ; Mon, 2 Jun 2014 10:35:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D80AF6E519; Mon, 2 Jun 2014 03:35:11 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from hydra.rus.uni-stuttgart.de (hydra.rus.uni-stuttgart.de [129.69.192.3]) by gabe.freedesktop.org (Postfix) with ESMTP id 69B3E6E519 for ; Mon, 2 Jun 2014 03:35:09 -0700 (PDT) Received: from localhost (localhost [127.0.0.1]) by hydra.rus.uni-stuttgart.de (Postfix) with ESMTP id 51ECE12C6A0; Mon, 2 Jun 2014 12:35:06 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= rus.uni-stuttgart.de; h=content-type:content-type:in-reply-to :references:subject:subject:user-agent:reply-to:from:from:date :date:message-id:received:received; s=dkim20100209; t= 1401705301; x=1403519702; bh=HpO58BsWrnX6XeXeKreFAnjGsLNExOTyYJJ iofCP130=; b=Dcp9tReUyjw9cZcryyzgNG+/UTol32JNVY4/WmjshdLfQo1WOmF pMebdPdCeCSzIf5LucszGqV3YcUOlVS8hn4SiEXAYerFYgbyDuf3b80R9a3BYppL IJwcXWSPsPPTTJQVGkzLKiT+viXoO3RooRQk9FU6m4IM1rZ7iVM3zqHA= X-Virus-Scanned: by amavisd-new at hydra.rus.uni-stuttgart.de Received: from hydra.rus.uni-stuttgart.de ([127.0.0.1]) by localhost (hydra.rus.uni-stuttgart.de [127.0.0.1]) (amavisd-new, port 10031) with ESMTP id cmK_0M_Fol9c; Mon, 2 Jun 2014 12:35:01 +0200 (CEST) Received: from [192.168.3.46] (p5B2EC7BC.dip0.t-ipconnect.de [91.46.199.188]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: ac105036) by hydra.rus.uni-stuttgart.de (Postfix) with ESMTPSA; Mon, 2 Jun 2014 12:35:00 +0200 (CEST) Message-ID: <538C5353.40001@rus.uni-stuttgart.de> Date: Mon, 02 Jun 2014 12:34:59 +0200 From: Thomas Richter User-Agent: Mozilla/5.0 (X11; Linux i686; rv:10.0.12) Gecko/20130116 Icedove/10.0.12 MIME-Version: 1.0 To: Daniel Vetter References: <53761A88.1060608@math.tu-berlin.de> <20140516144104.GE3473@nuc-i3427.alporthouse.com> <20140516150953.GN8790@phenom.ffwll.local> <20140516160454.GT27580@intel.com> <23914_1400259040_537641E0_23914_9298_1_20140516165034.GT8790@phenom.ffwll.local> <5387A473.5020102@rus.uni-stuttgart.de> <20140602082705.GJ19050@phenom.ffwll.local> In-Reply-To: <20140602082705.GJ19050@phenom.ffwll.local> Cc: intel-gfx Subject: [Intel-gfx] [PATCH] Align i830 watermark to cache lines X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list Reply-To: richter@rus.uni-stuttgart.de List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi folks, as by discussion, the problem with the i830 watermark problems is likely that the 830 requires the number of entries in the buffer to be a multiple of the cache line size. I provide hereby a small patch against intel_pm.c that performs the alignment for GEN2 chips. Tested on the Fujitsu S6010 and R31, seems to work fine here and generates reasonable watermarks that do not flicker. What is a bit unsatisfactory is that, due to the nature of the patch, the number of entries in the buffer is always rounded up (necessarily, to be conservative), even though for all practical configurations, the rounded up size is too large to fit into the buffer, and thus the rounding direction is "round down" instead of "round up" for all realistic settings. Anyhow, the stuff works. Greetings, Thomas From ee1210a1f49abaddc2c6c46cfb521db6ab08c261 Mon Sep 17 00:00:00 2001 From: thor Date: Sun, 1 Jun 2014 18:33:20 +0200 Subject: [PATCH] Align i830 watermark to cache lines. Signed-off-by: thor --- drivers/gpu/drm/i915/intel_pm.c | 38 +++++++++++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 1840d15..fbfd57c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -1489,6 +1489,22 @@ static void i965_update_wm(struct drm_crtc *unused_crtc) I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); } +static int round_to_lines(int watermark, int fifo_size, int line_size) +{ + int entries = fifo_size - watermark; + + if (entries < 0) + entries = 0; + + entries = DIV_ROUND_UP(entries, line_size); + while (entries > fifo_size) + entries -= line_size; + + watermark = fifo_size - line_size; + + return watermark; +} + static void i9xx_update_wm(struct drm_crtc *unused_crtc) { struct drm_device *dev = unused_crtc->dev; @@ -1520,6 +1536,12 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc) planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, wm_info, fifo_size, cpp, latency_ns); + + if (IS_GEN2(dev)) + planea_wm = round_to_lines(planea_wm, + fifo_size, + I830_FIFO_LINE_SIZE); + enabled = crtc; } else planea_wm = fifo_size - wm_info->guard_size; @@ -1536,6 +1558,12 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc) planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, wm_info, fifo_size, cpp, latency_ns); + + if (IS_GEN2(dev)) + planeb_wm = round_to_lines(planeb_wm, + fifo_size, + I830_FIFO_LINE_SIZE); + if (enabled == NULL) enabled = crtc; else @@ -1631,16 +1659,24 @@ static void i845_update_wm(struct drm_crtc *unused_crtc) const struct drm_display_mode *adjusted_mode; uint32_t fwater_lo; int planea_wm; + int fifo_size; crtc = single_enabled_crtc(dev); if (crtc == NULL) return; adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; + fifo_size = dev_priv->display.get_fifo_size(dev, 0); planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, &i845_wm_info, - dev_priv->display.get_fifo_size(dev, 0), + fifo_size, 4, latency_ns); + + planea_wm = round_to_lines(planea_wm, + fifo_size, + I830_FIFO_LINE_SIZE); + + fwater_lo = I915_READ(FW_BLC) & ~0xfff; fwater_lo |= (3<<8) | planea_wm; -- 1.7.10.4