From patchwork Sat Jun 7 20:37:06 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Richter X-Patchwork-Id: 4315971 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7AD0ABEEAA for ; Sat, 7 Jun 2014 20:37:26 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 427842014A for ; Sat, 7 Jun 2014 20:37:25 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 8BE4D20148 for ; Sat, 7 Jun 2014 20:37:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8831F6E4FF; Sat, 7 Jun 2014 13:37:22 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from medousa.rus.uni-stuttgart.de (medousa.rus.uni-stuttgart.de [129.69.192.4]) by gabe.freedesktop.org (Postfix) with ESMTP id 93EEB6E4FF for ; Sat, 7 Jun 2014 13:37:20 -0700 (PDT) Received: from localhost (localhost [127.0.0.1]) by medousa.rus.uni-stuttgart.de (Postfix) with ESMTP id 6DC3C37EF8; Sat, 7 Jun 2014 22:37:15 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= rus.uni-stuttgart.de; h=content-type:content-type:in-reply-to :references:subject:subject:user-agent:reply-to:from:from:date :date:message-id:received:received; s=dkim20100209; t= 1402173429; x=1403987830; bh=Onue2vsXQGjRF5FJ30Yn4bn51c/lTXHk9Mw Ujb3TX0s=; b=K8NHPgS0BFf3nRL9vSywWGydsisDFgGHuIoDNZ5cZWJmHlsyodq Y/mKvbBvPugRehanMAk5whRXk6jNb8+z6eqWwkr9BdAy1ob8CbyKjefEMbB3F8YV bRp6Nk4owxtfFpJU/vfgLwdrKmC3/3dNbJ9iHr0O+0ZnlypEMQOGzDhI= X-Virus-Scanned: by amavisd-new at medousa.rus.uni-stuttgart.de Received: from medousa.rus.uni-stuttgart.de ([127.0.0.1]) by localhost (medousa.rus.uni-stuttgart.de [127.0.0.1]) (amavisd-new, port 10031) with ESMTP id FHpKaA4WvFch; Sat, 7 Jun 2014 22:37:09 +0200 (CEST) Received: from [192.168.2.105] (p57971A02.dip0.t-ipconnect.de [87.151.26.2]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) (Authenticated sender: ac105036) by medousa.rus.uni-stuttgart.de (Postfix) with ESMTPSA; Sat, 7 Jun 2014 22:37:09 +0200 (CEST) Message-ID: <539377F2.20107@rus.uni-stuttgart.de> Date: Sat, 07 Jun 2014 22:37:06 +0200 From: Thomas Richter User-Agent: Mozilla/5.0 (X11; Linux i686; rv:10.0.12) Gecko/20130116 Icedove/10.0.12 MIME-Version: 1.0 To: Daniel Vetter References: <20140606170000.GL7416@phenom.ffwll.local> <1402083852-31461-1-git-send-email-ville.syrjala@linux.intel.com> <20140606201319.GU7416@phenom.ffwll.local> In-Reply-To: <20140606201319.GU7416@phenom.ffwll.local> Cc: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [Patch] Add minimum watermark level for I830 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list Reply-To: richter@rus.uni-stuttgart.de List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Dear Daniel, dear intel experts, please find a minimally-invasive patch to add a minimum watermark level to the current watermark logic. This fixes the flickering and video overlay crashes on 830M(G) chipsets. Note that this patch does not alter the watermark algorithm on any other family of the intel chipsets. Greetings, Thomas PS: What I do not understand about the current logic is that there is a "default watermark" level if the computed watermark is below zero, though computed watermarks can well drop below this default. The appended patch still allows that to be backwards compatible, though this construction sounds pretty weird to me. From 4ff44b36c3ca8ac0255700aaa8999e75efbf9598 Mon Sep 17 00:00:00 2001 From: thor Date: Sat, 7 Jun 2014 22:23:16 +0200 Subject: [PATCH] Added a min watermark level. Signed-off-by: thor --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++++++ 3 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 286f05c..442240b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3897,6 +3897,7 @@ enum punit_power_well { #define I915_FIFO_SIZE 95 #define I855GM_FIFO_SIZE 127 /* In cachelines */ #define I830_FIFO_SIZE 95 +#define I830_MIN_WM 8 #define VALLEYVIEW_MAX_WM 0xff #define G4X_MAX_WM 0x3f diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 78d4124..16d2f68 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -458,6 +458,7 @@ struct intel_plane { struct intel_watermark_params { unsigned long fifo_size; + unsigned long min_wm; unsigned long max_wm; unsigned long default_wm; unsigned long guard_size; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f83d1ff..ac8a832 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -866,6 +866,7 @@ static int i845_get_fifo_size(struct drm_device *dev, int plane) /* Pineview has different values for various configs */ static const struct intel_watermark_params pineview_display_wm = { .fifo_size = PINEVIEW_DISPLAY_FIFO, + .min_wm = 0, .max_wm = PINEVIEW_MAX_WM, .default_wm = PINEVIEW_DFT_WM, .guard_size = PINEVIEW_GUARD_WM, @@ -873,6 +874,7 @@ static const struct intel_watermark_params pineview_display_wm = { }; static const struct intel_watermark_params pineview_display_hplloff_wm = { .fifo_size = PINEVIEW_DISPLAY_FIFO, + .min_wm = 0, .max_wm = PINEVIEW_MAX_WM, .default_wm = PINEVIEW_DFT_HPLLOFF_WM, .guard_size = PINEVIEW_GUARD_WM, @@ -880,6 +882,7 @@ static const struct intel_watermark_params pineview_display_hplloff_wm = { }; static const struct intel_watermark_params pineview_cursor_wm = { .fifo_size = PINEVIEW_CURSOR_FIFO, + .min_wm = 0, .max_wm = PINEVIEW_CURSOR_MAX_WM, .default_wm = PINEVIEW_CURSOR_DFT_WM, .guard_size = PINEVIEW_CURSOR_GUARD_WM, @@ -887,6 +890,7 @@ static const struct intel_watermark_params pineview_cursor_wm = { }; static const struct intel_watermark_params pineview_cursor_hplloff_wm = { .fifo_size = PINEVIEW_CURSOR_FIFO, + .min_wm = 0, .max_wm = PINEVIEW_CURSOR_MAX_WM, .default_wm = PINEVIEW_CURSOR_DFT_WM, .guard_size = PINEVIEW_CURSOR_GUARD_WM, @@ -894,6 +898,7 @@ static const struct intel_watermark_params pineview_cursor_hplloff_wm = { }; static const struct intel_watermark_params g4x_wm_info = { .fifo_size = G4X_FIFO_SIZE, + .min_wm = 0, .max_wm = G4X_MAX_WM, .default_wm = G4X_MAX_WM, .guard_size = 2, @@ -901,6 +906,7 @@ static const struct intel_watermark_params g4x_wm_info = { }; static const struct intel_watermark_params g4x_cursor_wm_info = { .fifo_size = I965_CURSOR_FIFO, + .min_wm = 0, .max_wm = I965_CURSOR_MAX_WM, .default_wm = I965_CURSOR_DFT_WM, .guard_size = 2, @@ -908,6 +914,7 @@ static const struct intel_watermark_params g4x_cursor_wm_info = { }; static const struct intel_watermark_params valleyview_wm_info = { .fifo_size = VALLEYVIEW_FIFO_SIZE, + .min_wm = 0, .max_wm = VALLEYVIEW_MAX_WM, .default_wm = VALLEYVIEW_MAX_WM, .guard_size = 2, @@ -915,6 +922,7 @@ static const struct intel_watermark_params valleyview_wm_info = { }; static const struct intel_watermark_params valleyview_cursor_wm_info = { .fifo_size = I965_CURSOR_FIFO, + .min_wm = 0, .max_wm = VALLEYVIEW_CURSOR_MAX_WM, .default_wm = I965_CURSOR_DFT_WM, .guard_size = 2, @@ -922,6 +930,7 @@ static const struct intel_watermark_params valleyview_cursor_wm_info = { }; static const struct intel_watermark_params i965_cursor_wm_info = { .fifo_size = I965_CURSOR_FIFO, + .min_wm = 0, .max_wm = I965_CURSOR_MAX_WM, .default_wm = I965_CURSOR_DFT_WM, .guard_size = 2, @@ -929,6 +938,7 @@ static const struct intel_watermark_params i965_cursor_wm_info = { }; static const struct intel_watermark_params i945_wm_info = { .fifo_size = I945_FIFO_SIZE, + .min_wm = 0, .max_wm = I915_MAX_WM, .default_wm = 1, .guard_size = 2, @@ -936,6 +946,7 @@ static const struct intel_watermark_params i945_wm_info = { }; static const struct intel_watermark_params i915_wm_info = { .fifo_size = I915_FIFO_SIZE, + .min_wm = 0, .max_wm = I915_MAX_WM, .default_wm = 1, .guard_size = 2, @@ -943,6 +954,7 @@ static const struct intel_watermark_params i915_wm_info = { }; static const struct intel_watermark_params i830_wm_info = { .fifo_size = I855GM_FIFO_SIZE, + .min_wm = I830_MIN_WM, .max_wm = I915_MAX_WM, .default_wm = 1, .guard_size = 2, @@ -950,6 +962,7 @@ static const struct intel_watermark_params i830_wm_info = { }; static const struct intel_watermark_params i845_wm_info = { .fifo_size = I830_FIFO_SIZE, + .min_wm = I830_MIN_WM, .max_wm = I915_MAX_WM, .default_wm = 1, .guard_size = 2, @@ -1003,6 +1016,9 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz, wm_size = wm->max_wm; if (wm_size <= 0) wm_size = wm->default_wm; + if (wm_size < (long)wm->min_wm) + wm_size = wm->min_wm; + return wm_size; } -- 1.7.10.4