From patchwork Mon Jul 6 16:04:10 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wang, Zhi A" X-Patchwork-Id: 6730801 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id CFA9E9F319 for ; Tue, 7 Jul 2015 07:37:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D9534206E1 for ; Tue, 7 Jul 2015 07:37:01 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id B7B10206DF for ; Tue, 7 Jul 2015 07:37:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4977E6E338; Tue, 7 Jul 2015 00:37:00 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 2C3696E338 for ; Tue, 7 Jul 2015 00:36:59 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP; 07 Jul 2015 00:37:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,421,1432623600"; d="scan'208";a="741985321" Received: from dev-inno.bj.intel.com (HELO [10.238.135.77]) ([10.238.135.77]) by fmsmga001.fm.intel.com with ESMTP; 07 Jul 2015 00:36:58 -0700 Message-ID: <559AA6FA.2050405@intel.com> Date: Tue, 07 Jul 2015 00:04:10 +0800 From: Zhi Wang User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 To: Mika Kuoppala , Chris Wilson , bing.niu@intel.com References: <1435940854-24585-1-git-send-email-bing.niu@intel.com> <20150703090156.GC14231@nuc-i3427.alporthouse.com> <87oajto6n9.fsf@gaia.fi.intel.com> In-Reply-To: <87oajto6n9.fsf@gaia.fi.intel.com> Cc: intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH v2] drm/i915: Also perform gpu reset under execlist mode. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.0 required=5.0 tests=BAYES_00, DATE_IN_PAST_12_24, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi Chris and Mika: Thanks for the comments. I think that reset HW on module unload is an good idea. For now I think we should choose a proper position in the module unload sequence to reset HW. As GPU reset is render engine reset plus ring imrs(They will become to alll F after full GPU reset), I think a proper position should be after render and interrupt shutdown path. How about this place? base object refcount * will be 2 (+1 from object creation and +1 from do_switch()). * i915_gem_context_fini() will be called after gpu_idle() has switched ? 07/03/15 18:52, Mika Kuoppala ??: > Chris Wilson writes: > >> On Sat, Jul 04, 2015 at 12:27:34AM +0800, bing.niu@intel.com wrote: >>> From: "Niu,Bing" >>> >>> It is found that i915 will not reset gpu under execlist mode when >>> unload module. that will lead to some issues when unload/load module >>> with different submission mode. e.g. from execlist mode to ring >>> buffer mode via loading/unloading i915. Because HW is not in a reset >>> state and registers are not clean under such condition. >>> >>> Signed-off-by: Niu,Bing >> Reviewed-by: Chris Wilson >> >> I think we may end up doing the reset unconditionally in >> i915_driver_unload() because this argument holds for almost everything >> we setup. It's a bigger risk because of doing the gpu-reset on more >> machines, but module-unloading is a "developer feature"! > > And after that has been sorted, we should try reset on module load. > > This way initial state would be identical to after reset/unload state. > Now we have this situation that we don't know how much we are leaning on > bios on state setup. > > -Mika > >> The only issue is making sure that the reset is ordered appropriately. >> -Chris >> >> -- >> Chris Wilson, Intel Open Source Technology Centre >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index c5349fa..aeaf59e 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -1133,7 +1133,10 @@ int i915_driver_unload(struct drm_device *dev) pm_qos_remove_request(&dev_priv->pm_qos); i915_global_gtt_cleanup(dev); - + /* The only known way to stop the gpu from accessing the hw context is + * to reset it. Do this as the very last operation to avoid confusing + * other code, leading to spurious errors. */ + intel_gpu_reset(dev); intel_uncore_fini(dev); if (dev_priv->regs != NULL) pci_iounmap(dev->pdev, dev_priv->regs); diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index a7e58a8..376ee6b 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -373,11 +373,6 @@ void i915_gem_context_fini(struct drm_device *dev) int i; if (dctx->legacy_hw_ctx.rcs_state) { - /* The only known way to stop the gpu from accessing the hw context is - * to reset it. Do this as the very last operation to avoid confusing - * other code, leading to spurious errors. */ - intel_gpu_reset(dev); - /* When default context is created and switched to,