From patchwork Mon Jul 6 19:38:37 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wang, Zhi A" X-Patchwork-Id: 6732131 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0B7F6C05AC for ; Tue, 7 Jul 2015 11:11:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2A0DA2060C for ; Tue, 7 Jul 2015 11:11:30 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 2D6EC20607 for ; Tue, 7 Jul 2015 11:11:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A36726E9DA; Tue, 7 Jul 2015 04:11:28 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id BE2846E9DA for ; Tue, 7 Jul 2015 04:11:27 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP; 07 Jul 2015 04:11:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,422,1432623600"; d="scan'208";a="742103815" Received: from dev-inno.bj.intel.com (HELO [10.238.135.77]) ([10.238.135.77]) by fmsmga001.fm.intel.com with ESMTP; 07 Jul 2015 04:11:25 -0700 Message-ID: <559AD93D.8050503@intel.com> Date: Tue, 07 Jul 2015 03:38:37 +0800 From: Zhi Wang User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 To: Chris Wilson , Mika Kuoppala , bing.niu@intel.com, intel-gfx@lists.freedesktop.org References: <1435940854-24585-1-git-send-email-bing.niu@intel.com> <20150703090156.GC14231@nuc-i3427.alporthouse.com> <87oajto6n9.fsf@gaia.fi.intel.com> <559AA6FA.2050405@intel.com> <20150707085849.GW5312@nuc-i3427.alporthouse.com> In-Reply-To: <20150707085849.GW5312@nuc-i3427.alporthouse.com> Subject: Re: [Intel-gfx] [PATCH v2] drm/i915: Also perform gpu reset under execlist mode. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.0 required=5.0 tests=BAYES_00, DATE_IN_PAST_12_24, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi Chris: Thanks for the comments! I can understand that we're concerned about regressions, so this is why I think put this reset in module unload path looks much safer. For safety, maybe we should only reset GPU perhaps only when GEN >= 6? That looks much easier and safer, also combine execlist reset and power context reset. Or we just add this before i915_uncore_fini() inside i915_driver_unload()? This way looks much safer? How about this one? intel_uncore_fini(dev); if (dev_priv->regs != NULL) pci_iounmap(dev->pdev, dev_priv->regs); ? 07/07/15 16:58, Chris Wilson ??: > On Tue, Jul 07, 2015 at 12:04:10AM +0800, Zhi Wang wrote: >> Hi Chris and Mika: >> Thanks for the comments. I think that reset HW on module unload >> is an good idea. For now I think we should choose a proper position >> in the module unload sequence to reset HW. As GPU reset is render >> engine reset plus ring imrs(They will become to alll F after full >> GPU reset), I think a proper position should be after render and >> interrupt shutdown path. >> >> How about this place? >> >> diff --git a/drivers/gpu/drm/i915/i915_dma.c >> b/drivers/gpu/drm/i915/i915_dma.c >> index c5349fa..aeaf59e 100644 >> --- a/drivers/gpu/drm/i915/i915_dma.c >> +++ b/drivers/gpu/drm/i915/i915_dma.c >> @@ -1133,7 +1133,10 @@ int i915_driver_unload(struct drm_device *dev) >> pm_qos_remove_request(&dev_priv->pm_qos); >> >> i915_global_gtt_cleanup(dev); >> - >> + /* The only known way to stop the gpu from accessing the hw >> context is >> + * to reset it. Do this as the very last operation to avoid >> confusing >> + * other code, leading to spurious errors. */ >> + intel_gpu_reset(dev); > > That feels right. The comment is out-of-place now and needs expansion to > include other side effects for which the gpu reset is meritted. > > But this is a riskier patch since we now start doing unconditional > resets for gen3-gen5. Just requires more soak testing, but I would > prefer it as (1) add execlists reset, (2) combine execlists reset + > power context reset into a single unload reset. That way if we do get a > regression in doing the unload reset we can revert back to execlists > easily. > -Chris > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index c5349fa..81103af 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -1134,6 +1134,15 @@ int i915_driver_unload(struct drm_device *dev) i915_global_gtt_cleanup(dev); + /* + * Restore HW workload submission mode back to default mode when shutdown. + * It makes i915 module loading/unloading be able to switch between + * different workload submission mode on gen8+. And according to B-spec, + * the only way to reset HW workload submission mode to default mode is GPU reset. + */ + if (i915.enable_execlists) + intel_gpu_reset(dev); +