From patchwork Mon Jul 6 20:23:13 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wang, Zhi A" X-Patchwork-Id: 6732251 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D96119F380 for ; Tue, 7 Jul 2015 11:56:07 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EED91206F1 for ; Tue, 7 Jul 2015 11:56:06 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id F36F3206F0 for ; Tue, 7 Jul 2015 11:56:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 71FD56E9E4; Tue, 7 Jul 2015 04:56:05 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 11CE16E9E4 for ; Tue, 7 Jul 2015 04:56:03 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP; 07 Jul 2015 04:56:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,422,1432623600"; d="scan'208";a="742122924" Received: from dev-inno.bj.intel.com (HELO [10.238.135.77]) ([10.238.135.77]) by fmsmga001.fm.intel.com with ESMTP; 07 Jul 2015 04:56:01 -0700 Message-ID: <559AE3B1.9000300@intel.com> Date: Tue, 07 Jul 2015 04:23:13 +0800 From: Zhi Wang User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 To: Chris Wilson , Mika Kuoppala , bing.niu@intel.com, intel-gfx@lists.freedesktop.org References: <1435940854-24585-1-git-send-email-bing.niu@intel.com> <20150703090156.GC14231@nuc-i3427.alporthouse.com> <87oajto6n9.fsf@gaia.fi.intel.com> <559AA6FA.2050405@intel.com> <20150707085849.GW5312@nuc-i3427.alporthouse.com> <559AD93D.8050503@intel.com> <20150707111750.GB13251@nuc-i3427.alporthouse.com> In-Reply-To: <20150707111750.GB13251@nuc-i3427.alporthouse.com> Subject: Re: [Intel-gfx] [PATCH v2] drm/i915: Also perform gpu reset under execlist mode. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.0 required=5.0 tests=BAYES_00, DATE_IN_PAST_12_24, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi Chris: How about this one? :) base object refcount * will be 2 (+1 from object creation and +1 from do_switch()). * i915_gem_context_fini() will be called after gpu_idle() has switched ? 07/07/15 19:17, Chris Wilson ??: > On Tue, Jul 07, 2015 at 03:38:37AM +0800, Zhi Wang wrote: >> Hi Chris: >> Thanks for the comments! I can understand that we're concerned >> about regressions, so this is why I think put this reset in module >> unload path looks much safer. For safety, maybe we should only reset >> GPU perhaps only when GEN >= 6? That looks much easier and safer, >> also combine execlist reset and power context reset. >> >> Or we just add this before i915_uncore_fini() inside >> i915_driver_unload()? This way looks much safer? >> >> How about this one? > > No, if we are just targetting execlists, then disabling it in > cleanup_ringbuffers as before is the cleanest (as that is the opposite > stage to where we enable them). > > The reset in i915_driver_unload() is preferred to replace all the resets > required during unload. It is safe to move the context reset here as we > do not disturb the GTT state between unpining the context and here. > Making it conditional on gen>=5 is probably a good first step. > -Chris > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index c5349fa..013039e 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -1134,6 +1134,21 @@ int i915_driver_unload(struct drm_device *dev) i915_global_gtt_cleanup(dev); + /* + * The only known way to stop the gpu from accessing the hw context in + * graphics memory space is to reset it. Do this as the very last + * operation to avoid confusing other code, leading to spurious errors. + * + * Besides, we also need to restore HW workload submission mode back + * to default mode when shutdown i915. + * + * It makes i915 module loading/unloading be able to switch between + * different workload submission mode on gen8+. And according to B-spec, + * the only way to reset HW workload submission mode to default mod is GPU reset. + */ + if (INTEL_INFO(dev)->gen >= 5) + intel_gpu_reset(dev); + intel_uncore_fini(dev); if (dev_priv->regs != NULL) pci_iounmap(dev->pdev, dev_priv->regs); diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index a7e58a8..376ee6b 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -373,11 +373,6 @@ void i915_gem_context_fini(struct drm_device *dev) int i; if (dctx->legacy_hw_ctx.rcs_state) { - /* The only known way to stop the gpu from accessing the hw context is - * to reset it. Do this as the very last operation to avoid confusing - * other code, leading to spurious errors. */ - intel_gpu_reset(dev); - /* When default context is created and switched to,