| Message ID | 589991D9.9040609@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Feb 07, 2017 at 05:22:33PM +0800, Zhi Wang wrote: > Hi Chris: > Thanks for the explanation! :P Have you already sent the patch > to keep PD structure under aliasing PPGTT mode? I tried > drm-intel-nightly branch and still got kernel panic under aliasing > PPGTT mode. T_T It's on the list, just starting to get reviews. > > I fixed it like this, is this acceptable as a hot fix? If it's > acceptable as a hot fix, I can send a patch. :P Is one of the patches. The only difference is that we don't actually want to run alloc_va_range for gen6/7 as that is static. A minor detail. -Chris
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 22b3374..21e06c9 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2658,6 +2658,19 @@ static int aliasing_gtt_bind_vma(struct i915_vma *vma, if (vma->obj->gt_ro) pte_flags |= PTE_READ_ONLY; + if (flags & I915_VMA_LOCAL_BIND) { + struct i915_hw_ppgtt *appgtt = i915->mm.aliasing_ppgtt; + + ret = appgtt->base.allocate_va_range(&appgtt->base, + vma->node.start, + vma->node.size); + if (ret) + return ret; + + appgtt->base.insert_entries(&appgtt->base, + vma->pages, vma->node.start, + cache_level, pte_flags); + } if (flags & I915_VMA_GLOBAL_BIND) {
Hi Chris: Thanks for the explanation! :P Have you already sent the patch to keep PD structure under aliasing PPGTT mode? I tried drm-intel-nightly branch and still got kernel panic under aliasing PPGTT mode. T_T I fixed it like this, is this acceptable as a hot fix? If it's acceptable as a hot fix, I can send a patch. :P intel_runtime_pm_get(i915); @@ -2666,14 +2679,6 @@ static int aliasing_gtt_bind_vma(struct i915_vma *vma, cache_level, pte_flags); intel_runtime_pm_put(i915); } - - if (flags & I915_VMA_LOCAL_BIND) { - struct i915_hw_ppgtt *appgtt = i915->mm.aliasing_ppgtt; - appgtt->base.insert_entries(&appgtt->base, - vma->pages, vma->node.start, - cache_level, pte_flags); - } - return 0; } On 02/06/17 19:38, Chris Wilson wrote: > On Mon, Feb 06, 2017 at 07:03:39PM +0800, Zhi Wang wrote: >> Thanks for the merging. I guess that with your patches of keeping PD >> structure under aliasing PPGTT mode in 32bit page table, the amount >> of PDPs will not change anymore under aliasing PPGTT mode. :P > > Yes. That's the idea atm, we will preallocate the aliasing table > and then keep the tree intact. The only disadvantage with gen8+ aliasing > mode (compared to gen6) will be that we still have to walk the va range > to pin the tree so that when we call clear_range afterwards we don't > reap. The benefit from my pov, is that the special case for > aliasing_ppgtt is within the aliasing_ppgtt code and not in the common > code (which should be optimised for full-ppgtt as that is the > default/typical use). > -Chris >