diff mbox series

[15/16] drm/i915: pass dev_priv explicitly to PRIMCNSTALPHA

Message ID 783477b86f4d53849775cbf690bb8b9042792a66.1716469091.git.jani.nikula@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: dev_priv fixes for i9xx_plane_regs.h/intel_color_regs.h | expand

Commit Message

Jani Nikula May 23, 2024, 12:59 p.m. UTC 
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PRIMCNSTALPHA register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/i9xx_plane.c      | 3 ++-
 drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 4 ++--
 2 files changed, 4 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 82cb393a0a22..5c8778865156 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -478,7 +478,8 @@  static void i9xx_plane_update_arm(struct intel_plane *plane,
 				  PRIM_POS_Y(crtc_y) | PRIM_POS_X(crtc_x));
 		intel_de_write_fw(dev_priv, PRIMSIZE(dev_priv, i9xx_plane),
 				  PRIM_HEIGHT(crtc_h - 1) | PRIM_WIDTH(crtc_w - 1));
-		intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0);
+		intel_de_write_fw(dev_priv,
+				  PRIMCNSTALPHA(dev_priv, i9xx_plane), 0);
 	}
 
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index 8d45c879e74a..a2ba55fa2b30 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -101,8 +101,8 @@ 
 #define   PRIM_WIDTH_MASK	REG_GENMASK(15, 0)
 #define   PRIM_WIDTH(w)		REG_FIELD_PREP(PRIM_WIDTH_MASK, (w))
 
-#define _PRIMCNSTALPHA_A	0x60a10
-#define PRIMCNSTALPHA(plane)	_MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A)
+#define _PRIMCNSTALPHA_A		0x60a10
+#define PRIMCNSTALPHA(dev_priv, plane)	_MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A)
 #define   PRIM_CONST_ALPHA_ENABLE	REG_BIT(31)
 #define   PRIM_CONST_ALPHA_MASK		REG_GENMASK(7, 0)
 #define   PRIM_CONST_ALPHA(alpha)	REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha))