From patchwork Tue Apr 26 04:09:19 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 8934691 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1D9669F1C1 for ; Tue, 26 Apr 2016 04:09:46 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 22CEF20166 for ; Tue, 26 Apr 2016 04:09:45 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id E671C2014A for ; Tue, 26 Apr 2016 04:09:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E71516E174; Tue, 26 Apr 2016 04:09:40 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 2C9DC6E72C for ; Tue, 26 Apr 2016 04:09:39 +0000 (UTC) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP; 25 Apr 2016 21:09:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,535,1455004800"; d="scan'208";a="952913028" Received: from orsmsx104.amr.corp.intel.com ([10.22.225.131]) by fmsmga001.fm.intel.com with ESMTP; 25 Apr 2016 21:09:21 -0700 Received: from orsmsx106.amr.corp.intel.com ([169.254.1.174]) by ORSMSX104.amr.corp.intel.com ([169.254.4.95]) with mapi id 14.03.0248.002; Mon, 25 Apr 2016 21:09:19 -0700 From: "Navare, Manasi D" To: "Shrivastava, Shubhangi" , "intel-gfx@lists.freedesktop.org" Thread-Topic: [Intel-gfx] [PATCH 2/5] drm/i915: Read test values for lane_count and link_rate Thread-Index: AQHRnsuVLN3IyXJH7UGrTbe+XaC/Gp+boGAQ Date: Tue, 26 Apr 2016 04:09:19 +0000 Message-ID: <87E1A67218970041879FDD2045F7145D02A67E94@ORSMSX106.amr.corp.intel.com> References: <1461572670-32421-1-git-send-email-shubhangi.shrivastava@intel.com> <1461572670-32421-2-git-send-email-shubhangi.shrivastava@intel.com> In-Reply-To: <1461572670-32421-2-git-send-email-shubhangi.shrivastava@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.22.254.140] MIME-Version: 1.0 Cc: "Shrivastava, Shubhangi" Subject: Re: [Intel-gfx] [PATCH 2/5] drm/i915: Read test values for lane_count and link_rate X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The automated test request for link training needs to start the link training with the requested link rate and lane count. So after reading the TEST LANE COUNT and TEST LINK RATE values, it needs to call intel_dp_start_link_train() also. How is the automated link train being tested currently? Could you add some details of the automated testing (test numbers from the CTS usite) in the commit message. Regards, Manasi Navare Graphics Kernel Developer OTC, Intel Corporation -----Original Message----- From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Shubhangi Shrivastava Sent: Monday, April 25, 2016 1:24 AM To: intel-gfx@lists.freedesktop.org Cc: Shrivastava, Shubhangi Subject: [Intel-gfx] [PATCH 2/5] drm/i915: Read test values for lane_count and link_rate During automated test request for link training we are supposed to read the TEST_LANE_COUNT and TEST_LINK_RATE dpcd registers and use respective values in the next link training. This patch adds reading and updating of these values. Signed-off-by: Sivakumar Thulasimani Signed-off-by: Shubhangi Shrivastava --- drivers/gpu/drm/i915/intel_dp.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 1b26c59..387800b 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -4010,9 +4010,34 @@ intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) return true; } +/* + * This function reads TEST_LANE_COUNT & TEST_LINK_RATE and updates + * them to cached dpcd values, thus the new values are implicitly + * used by rest of the code without need to be aware of the change. + */ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) { uint8_t test_result = DP_TEST_ACK; + uint8_t dpcd_val, ret; + + ret = drm_dp_dpcd_read(&intel_dp->aux, + DP_TEST_LANE_COUNT, + &dpcd_val, 1); + + /* update values only if read returned 1 byte */ + if (ret == 1) { + dpcd_val &= DP_MAX_LANE_COUNT_MASK; + intel_dp->dpcd[DP_MAX_LANE_COUNT] &= ~(DP_MAX_LANE_COUNT_MASK); + intel_dp->dpcd[DP_MAX_LANE_COUNT] |= dpcd_val; + } + + ret = drm_dp_dpcd_read(&intel_dp->aux, + DP_TEST_LINK_RATE, + &dpcd_val, 1); + + if (ret == 1) + intel_dp->dpcd[DP_MAX_LINK_RATE] = dpcd_val; + return test_result; } -- 2.6.1