From patchwork Wed Sep 15 17:10:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Yokoyama, Caz" X-Patchwork-Id: 12496977 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41FCAC433F5 for ; Wed, 15 Sep 2021 17:13:40 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0C98860F44 for ; Wed, 15 Sep 2021 17:13:40 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 0C98860F44 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 70B3E6E994; Wed, 15 Sep 2021 17:13:39 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 47D116E994 for ; Wed, 15 Sep 2021 17:13:38 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10108"; a="209612192" X-IronPort-AV: E=Sophos;i="5.85,296,1624345200"; d="scan'208";a="209612192" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Sep 2021 10:10:58 -0700 X-IronPort-AV: E=Sophos;i="5.85,296,1624345200"; d="scan'208";a="553383986" Received: from mgirach-mobl.amr.corp.intel.com (HELO cyokoyam-desk2.intel.com) ([10.212.7.223]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Sep 2021 10:10:57 -0700 From: "Yokoyama, Caz" To: intel-gfx@lists.freedesktop.org Cc: Caz Yokoyama , Matt Roper , Radhakrishna Sripada , Jose Roberto de Souza Date: Wed, 15 Sep 2021 10:10:39 -0700 Message-Id: <8b54dd068cbd8b7448a1a2b5b6c6c962f576a6f2.1631725784.git.caz.yokoyama@intel.com> X-Mailer: git-send-email 2.31.1.362.g311531c9de MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/1] drm/i915/adlp: Keep hardware default dbox B credits X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Caz Yokoyama Do not overwrite registers that don't need to change from default value to 0. bspec 49213 Cc: Radhakrishna Sripada Cc: José Roberto de Souza Cc: Matt Roper Signed-off-by: Caz Yokoyama Reviewed-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_display.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a7ca38613f89..9190a3bc28a8 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2955,18 +2955,23 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - u32 val; + u32 val = intel_de_read(dev_priv, PIPE_MBUS_DBOX_CTL(pipe)); + val &= ~MBUS_DBOX_A_CREDIT_MASK; /* Wa_22010947358:adl-p */ if (IS_ALDERLAKE_P(dev_priv)) - val = joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4); + val |= joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4); else - val = MBUS_DBOX_A_CREDIT(2); + val |= MBUS_DBOX_A_CREDIT(2); - if (DISPLAY_VER(dev_priv) >= 12) { + if (IS_ALDERLAKE_P(dev_priv)) { + /* Take effect hardware default MBUS_DBOX_B_CREDIT(8) */ + } else if (DISPLAY_VER(dev_priv) >= 12) { + val &= ~(MBUS_DBOX_BW_CREDIT_MASK | MBUS_DBOX_B_CREDIT_MASK); val |= MBUS_DBOX_BW_CREDIT(2); val |= MBUS_DBOX_B_CREDIT(12); } else { + val &= ~(MBUS_DBOX_BW_CREDIT_MASK | MBUS_DBOX_B_CREDIT_MASK); val |= MBUS_DBOX_BW_CREDIT(1); val |= MBUS_DBOX_B_CREDIT(8); }