diff mbox

drm/i915: remove intermediate link rate entries for CHV

Message ID D5D6254030DBC644B6EE58B333BFBB1E9BC92240@ORSMSX112.amr.corp.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Hindman, Gavin July 30, 2015, 5:18 p.m. UTC
This applies to all CHV derivatives, including BSW?

Gavin Hindman


-----Original Message-----
From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Sivakumar Thulasimani
Sent: Thursday, July 30, 2015 1:45 AM
To: ville.syrjala@linux.intel.com; intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] drm/i915: remove intermediate link rate entries for CHV

From: "Thulasimani,Sivakumar" <sivakumar.thulasimani@intel.com>

CHV does not support intermediate link rates nor does it support HBR2. This patch removes those entries and returns HBR as the max link rate supported on CHV platform.

Signed-off-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c |   11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

--
1.7.9.5

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Comments

Sivakumar Thulasimani July 31, 2015, 1:25 a.m. UTC | #1
On 7/30/2015 10:48 PM, Hindman, Gavin wrote:
> This applies to all CHV derivatives, including BSW?
>
> Gavin Hindman
yes, this will apply to all CHV derivatives.
> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Sivakumar Thulasimani
> Sent: Thursday, July 30, 2015 1:45 AM
> To: ville.syrjala@linux.intel.com; intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH] drm/i915: remove intermediate link rate entries for CHV
>
> From: "Thulasimani,Sivakumar" <sivakumar.thulasimani@intel.com>
>
> CHV does not support intermediate link rates nor does it support HBR2. This patch removes those entries and returns HBR as the max link rate supported on CHV platform.
>
> Signed-off-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_dp.c |   11 +++--------
>   1 file changed, 3 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 898dc74..5c68b17 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -95,9 +95,6 @@ static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
>   				  324000, 432000, 540000 };
>   static const int skl_rates[] = { 162000, 216000, 270000,
>   				  324000, 432000, 540000 };
> -static const int chv_rates[] = { 162000, 202500, 210000, 216000,
> -				 243000, 270000, 324000, 405000,
> -				 420000, 432000, 540000 };
>   static const int default_rates[] = { 162000, 270000, 540000 };
>   
>   /**
> @@ -1186,15 +1183,13 @@ intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
>   	} else if (IS_SKYLAKE(dev)) {
>   		*source_rates = skl_rates;
>   		return ARRAY_SIZE(skl_rates);
> -	} else if (IS_CHERRYVIEW(dev)) {
> -		*source_rates = chv_rates;
> -		return ARRAY_SIZE(chv_rates);
>   	}
>   
>   	*source_rates = default_rates;
>   
> -	if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
> -		/* WaDisableHBR2:skl */
> +	/* WaDisableHBR2:skl */
> +	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
> +		IS_CHERRYVIEW(dev))
>   		return (DP_LINK_BW_2_7 >> 3) + 1;
>   	else if (INTEL_INFO(dev)->gen >= 8 ||
>   	    (IS_HASWELL(dev) && !IS_HSW_ULX(dev)))
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 898dc74..5c68b17 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -95,9 +95,6 @@  static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
 				  324000, 432000, 540000 };
 static const int skl_rates[] = { 162000, 216000, 270000,
 				  324000, 432000, 540000 };
-static const int chv_rates[] = { 162000, 202500, 210000, 216000,
-				 243000, 270000, 324000, 405000,
-				 420000, 432000, 540000 };
 static const int default_rates[] = { 162000, 270000, 540000 };
 
 /**
@@ -1186,15 +1183,13 @@  intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
 	} else if (IS_SKYLAKE(dev)) {
 		*source_rates = skl_rates;
 		return ARRAY_SIZE(skl_rates);
-	} else if (IS_CHERRYVIEW(dev)) {
-		*source_rates = chv_rates;
-		return ARRAY_SIZE(chv_rates);
 	}
 
 	*source_rates = default_rates;
 
-	if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
-		/* WaDisableHBR2:skl */
+	/* WaDisableHBR2:skl */
+	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
+		IS_CHERRYVIEW(dev))
 		return (DP_LINK_BW_2_7 >> 3) + 1;
 	else if (INTEL_INFO(dev)->gen >= 8 ||
 	    (IS_HASWELL(dev) && !IS_HSW_ULX(dev)))