Message ID | D908B1B9E708C047A32444772B58AE882218B1@SHSMSX101.ccr.corp.intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
On Tue, Aug 21, 2012 at 03:06:02AM +0000, Xu, Anhua wrote: > From 952c95621b5fd95a629c36017c36ac9e6c40e839 Mon Sep 17 00:00:00 2001 > From: Anhua Xu <anhua.xu@intel.com> > Date: Tue, 21 Aug 2012 11:00:57 +0800 > Subject: [PATCH] drm/i915: fix reassignment of variable "intel_dp->DP" > > This little regression was introduced by: > commit 417e822deee1d2bcd8a8a60660c40a0903713f2b > Author: Keith Packard <keithp@keithp.com> > Date: Tue Nov 1 19:54:11 2011 -0700 > > drm/i915: Treat PCH eDP like DP in most places > > PCH eDP has many of the same needs as regular PCH DP connections, > including the DP_CTl bit settings, the TRANS_DP_CTL register. > > The reachable tag for this commit is: v3.1-5461-g417e822 > > Signed-off-by: Anhua Xu <anhua.xu@intel.com> Queued for -next, thanks for the patch. Note that your patch description is a bit thin on details and the diff itself also doesn't tell much (since the 2nd, duplicate line is just right out off the context). Which made reviewing this a bit confusing for a short time. I've improved the diff by killing a superflous line (that way the 2nd assignment shows up) and explained in the commit message what's going on. -Daniel
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index a6c426a..c060231 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -882,7 +882,6 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, * supposed to be read-only. */ intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; - intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; /* Handle DP bits in common between all three register formats */