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[66/67] drm/i915/cnl: LSPCON support is gen9+

Message ID FF3DDC77922A8A4BB08A3BC48A1EA8CB412A17BB@BGSMSX101.gar.corp.intel.com (mailing list archive)
State New, archived
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Commit Message

Sharma, Shashank April 7, 2017, 5:54 a.m. UTC 
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>

Regards
Shashank
-----Original Message-----
From: Vivi, Rodrigo 
Sent: Thursday, April 6, 2017 10:16 PM
To: intel-gfx@lists.freedesktop.org
Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>; Sharma, Shashank <shashank.sharma@intel.com>
Subject: [PATCH 66/67] drm/i915/cnl: LSPCON support is gen9+

There is no platform specific change needed for LSPCON support on Cannonlake. So let's make it gen9+.

Cc: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--
1.9.1
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Patch

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index fc787dd..bf336bd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2986,7 +2986,7 @@  static inline struct scatterlist *__sg_next(struct scatterlist *sg)
 
 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
 
-#define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))
+#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
 
 /* DPF == dynamic parity feature */
 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)