From patchwork Tue Jun 4 15:25:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13685528 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7FD94C25B78 for ; Tue, 4 Jun 2024 15:28:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C025D10E4EC; Tue, 4 Jun 2024 15:28:29 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="njZ9v27K"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 452FB10E4F2 for ; Tue, 4 Jun 2024 15:28:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1717514904; x=1749050904; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=R1NSoOkmg9iNSdBAaT0rXXomAUiNSlBAFwEFQdGlLYs=; b=njZ9v27KqN7S0DGk4LtxuNAGRMEweydFjukAsn+rI5sLFjvc9AuNkFJU 2Zu4O0ed5UiefG0OakTw6YpU+FCBEgXfwEyce8sudmU+16Zm2TR0QeRic VhzDOaf5oAGUW2Sjnw5rgJzRJUKqtVCroIfeEcjuh/MKkQzuXcBhPfteL W1HRTJ2ZPYB7oXsg0uFZsW4pMCuP+RKYJ2GkQZTxg6mXEAM1It0sXFhc4 rFYeJIDud9wpXbdYElFtNzvxuMGXYEzlAsssmqAGNiWI2l4aJ67Y0w/cj wvZXO4GFXVI+D5aZGQ+yP79RXbJvpi5LoP5EvHCM7J+TK9nBBr1el7AzN A==; X-CSE-ConnectionGUID: O5urgZ2dSm2Ra3Lsz+tFbw== X-CSE-MsgGUID: Vb6xEy8NSJq6fUOmZZPfnw== X-IronPort-AV: E=McAfee;i="6600,9927,11093"; a="14225645" X-IronPort-AV: E=Sophos;i="6.08,214,1712646000"; d="scan'208";a="14225645" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jun 2024 08:28:24 -0700 X-CSE-ConnectionGUID: VPJeHEicTuKXKPakzpG1fA== X-CSE-MsgGUID: FuubqNraToqgHulU/dPknQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,214,1712646000"; d="scan'208";a="37278045" Received: from mwiniars-desk2.ger.corp.intel.com (HELO localhost) ([10.245.246.123]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jun 2024 08:28:22 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com Subject: [PATCH 24/65] drm/i915: pass dev_priv explicitly to ICL_PIPESTATUS Date: Tue, 4 Jun 2024 18:25:42 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the ICL_PIPESTATUS register macro. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/i915/display/intel_fifo_underrun.c | 9 ++++++--- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c index 401726f466c0..e5e4ca7cc499 100644 --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c @@ -209,7 +209,8 @@ static void bdw_set_fifo_underrun_reporting(struct drm_device *dev, if (enable) { if (DISPLAY_VER(dev_priv) >= 11) - intel_de_write(dev_priv, ICL_PIPESTATUS(pipe), + intel_de_write(dev_priv, + ICL_PIPESTATUS(dev_priv, pipe), icl_pipe_status_underrun_mask(dev_priv)); bdw_enable_pipe_irq(dev_priv, pipe, mask); @@ -418,9 +419,11 @@ void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, * the underrun was caused by the downstream port. */ if (DISPLAY_VER(dev_priv) >= 11) { - underruns = intel_de_read(dev_priv, ICL_PIPESTATUS(pipe)) & + underruns = intel_de_read(dev_priv, + ICL_PIPESTATUS(dev_priv, pipe)) & icl_pipe_status_underrun_mask(dev_priv); - intel_de_write(dev_priv, ICL_PIPESTATUS(pipe), underruns); + intel_de_write(dev_priv, ICL_PIPESTATUS(dev_priv, pipe), + underruns); } if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1b2c0d650bff..cbe109973f57 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1927,7 +1927,7 @@ #define PIPE_MISC2(pipe) _MMIO_PIPE(pipe, _PIPE_MISC2_A, _PIPE_MISC2_B) #define _ICL_PIPE_A_STATUS 0x70058 -#define ICL_PIPESTATUS(pipe) _MMIO_PIPE2(dev_priv, pipe, _ICL_PIPE_A_STATUS) +#define ICL_PIPESTATUS(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _ICL_PIPE_A_STATUS) #define PIPE_STATUS_UNDERRUN REG_BIT(31) #define PIPE_STATUS_SOFT_UNDERRUN_XELPD REG_BIT(28) #define PIPE_STATUS_HARD_UNDERRUN_XELPD REG_BIT(27)