From patchwork Wed Jun 29 15:25:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12900305 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3D111C43334 for ; Wed, 29 Jun 2022 15:25:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3EB1910E35D; Wed, 29 Jun 2022 15:25:36 +0000 (UTC) Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0CD0910E3AB; Wed, 29 Jun 2022 15:25:33 +0000 (UTC) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id BC5A1B824BC; Wed, 29 Jun 2022 15:25:31 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7F761C34114; Wed, 29 Jun 2022 15:25:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656516330; bh=WfCqVL/HkSy9hkFb7D4vO+nAC41+jUaURlFZDbgG3v4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IRx39RV40TrGV8qKo3powlOOuJ+tBL7T9QXd+/oSz3zRcIFKlEshJoKdCH4iOYjv1 0iTPGzr+8Absf0vnUJCvFw8jTiCy3t2Z6490sH6TOO8Jw48hv6p+9nJOpailhc4EjM YixY6a7BVJO5imxUkRYh5MHuv1mictKpOYg8OFMxNf5SpeX/smRY0X7Vh5lF18pM8h OUASz1u7dWfJ2OvuRKS80bNkX/+HtGEodiw5gk+cxXCXG4+4FimqlraqpPaoHtcPSz /HCuNIZ5KYFYCKo7wCDK4Qi7YgZaKujpcK3Jnt0mxRsinZi5h2WBxq8ZldFQ2swy9P BbkmMNBJS+zag== Received: from mchehab by mail.kernel.org with local (Exim 4.95) (envelope-from ) id 1o6ZZH-005hFO-PX; Wed, 29 Jun 2022 16:25:27 +0100 From: Mauro Carvalho Chehab To: Date: Wed, 29 Jun 2022 16:25:26 +0100 Message-Id: X-Mailer: git-send-email 2.36.1 In-Reply-To: References: MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 3/3] drm/i915/gt: Serialize TLB invalidates with GT resets X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andi Shyti , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , David Airlie , dri-devel@lists.freedesktop.org, Lucas De Marchi , linux-kernel@vger.kernel.org, Chris Wilson , Rodrigo Vivi , Dave Airlie , stable@vger.kernel.org, Mauro Carvalho Chehab , intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Chris Wilson Avoid trying to invalidate the TLB in the middle of performing an engine reset, as this may result in the reset timing out. Currently, the TLB invalidate is only serialised by its own mutex, forgoing the uncore lock, but we can take the uncore->lock as well to serialise the mmio access, thereby serialising with the GDRST. Tested on a NUC5i7RYB, BIOS RYBDWi35.86A.0380.2019.0517.1530 with i915 selftest/hangcheck. Cc: stable@vger.kernel.org Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store") Reported-by: Mauro Carvalho Chehab Tested-by: Mauro Carvalho Chehab Reviewed-by: Mauro Carvalho Chehab Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Acked-by: Thomas Hellström Reviewed-by: Andi Shyti Signed-off-by: Mauro Carvalho Chehab --- See [PATCH v2 0/3] at: https://lore.kernel.org/all/cover.1656516220.git.mchehab@kernel.org/ drivers/gpu/drm/i915/gt/intel_gt.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 30c60cd960e8..7e57a90b4095 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -952,6 +952,8 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) mutex_lock(>->tlb_invalidate_lock); intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); + spin_lock_irq(&uncore->lock); /* seralise invalidate with GT reset */ + awake = 0; for_each_engine(engine, gt, id) { struct reg_and_bit rb; @@ -967,6 +969,8 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) awake |= engine->mask; } + spin_unlock_irq(&uncore->lock); + for_each_engine_masked(engine, gt, awake, tmp) { struct reg_and_bit rb;