From patchwork Fri Oct 13 00:19:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michel Thierry X-Patchwork-Id: 10003317 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8BF9960325 for ; Fri, 13 Oct 2017 00:19:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7E01F28DC5 for ; Fri, 13 Oct 2017 00:19:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 72D1D28F0A; Fri, 13 Oct 2017 00:19:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id F36DD28DC5 for ; Fri, 13 Oct 2017 00:19:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9D54A6E9CF; Fri, 13 Oct 2017 00:19:57 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id B4B606E9CF for ; Fri, 13 Oct 2017 00:19:55 +0000 (UTC) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Oct 2017 17:19:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.43,368,1503385200"; d="scan'208";a="159948058" Received: from relo-linux-11.sc.intel.com (HELO [10.3.160.161]) ([10.3.160.161]) by orsmga005.jf.intel.com with ESMTP; 12 Oct 2017 17:19:51 -0700 From: Michel Thierry To: Daniele Ceraolo Spurio , =?UTF-8?Q?Micha=c5=82_Winiarski?= , intel-gfx@lists.freedesktop.org References: <20171009145258.23303-1-michal.winiarski@intel.com> <20171009145258.23303-3-michal.winiarski@intel.com> <6e22485c-5948-27b8-b197-3683d2b1175e@intel.com> Message-ID: Date: Thu, 12 Oct 2017 17:19:51 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US Subject: Re: [Intel-gfx] [PATCH 02/12] drm/i915/guc: Allocate separate shared data object for GuC communication X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP On 12/10/17 13:35, Michel Thierry wrote: > On 09/10/17 15:35, Michel Thierry wrote: >> On 10/9/2017 11:41 AM, Daniele Ceraolo Spurio wrote: >>> >>> >>> On 09/10/17 07:52, Michał Winiarski wrote: >>>> We were using first page of kernel context render state for sharing >>>> data >>>> with GuC. While it's justified by the fact that those pages are not >>>> used >>>> (note, GuC still enforces this layout and refuses to work if we remove >>>> the extra page in front), it's also confusing (why are we using this >>>> particular page?). Let's allocate a separate object instead. >>>> >>>> Suggested-by: Daniele Ceraolo Spurio >>>> Signed-off-by: Michał Winiarski >>>> Cc: Chris Wilson >>>> Cc: Daniele Ceraolo Spurio >>>> Cc: Jeff McGee >>>> Cc: Michal Wajdeczko >>>> Cc: Oscar Mateo >>> >>> +Michel (engine and watchdog reset with GuC use the shared page) >>> >>>> --- >>>> drivers/gpu/drm/i915/i915_guc_submission.c | 36 >>>> +++++++++++++++++++++++++++++- >>>> drivers/gpu/drm/i915/intel_guc.c | 8 ++----- >>>> drivers/gpu/drm/i915/intel_guc.h | 2 ++ >>>> 3 files changed, 39 insertions(+), 7 deletions(-) >>>> >>>> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c >>>> b/drivers/gpu/drm/i915/i915_guc_submission.c >>>> index 8983d53af229..30f026566001 100644 >>>> --- a/drivers/gpu/drm/i915/i915_guc_submission.c >>>> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c >>>> @@ -437,6 +437,33 @@ static void guc_stage_desc_fini(struct >>>> intel_guc *guc, >>>> memset(desc, 0, sizeof(*desc)); >>>> } >>>> +static int guc_shared_data_create(struct intel_guc *guc) >>>> +{ >>>> + struct i915_vma *vma; >>>> + void *vaddr; >>>> + >>>> + vma = intel_guc_allocate_vma(guc, PAGE_SIZE); >>>> + if (IS_ERR(vma)) >>>> + return PTR_ERR(vma); >>>> + >>>> + vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); >>>> + if (IS_ERR(vaddr)) { >>>> + i915_vma_unpin_and_release(&vma); >>>> + return PTR_ERR(vaddr); >>>> + } >>>> + >>>> + guc->shared_data = vma; >>>> + guc->shared_data_vaddr = vaddr; >> >> Hi, >> >> Allocating the shared_data until this point (i915_guc_submission_init) >> will be too late for GuC's watchdog. >> >> GuC watchdog happens without i915 knowledge, so we have to pass this >> shared_data_offset during guc_params_init (in params[9] for the >> curious) instead of a h2g command; and the GuC parameters block has >> this note: "These parameters are read by the firmware on startup and >> cannot be changed thereafter". >> >> Michał, if you plan to send another version of this, could you move it >> to guc_params_init? It isn't a big issue, I can just move it when we >> have an open source user and can upstream GuC watchdog. >> >> Thanks, >> >> -Michel >> > > Ignore my previous reply, this is already being allocated before > guc_params_init as it is. > > Reviewed-by: Michel Thierry > I spoke too soon (and sorry for all the spam), the kernel_context is now redundant code and should be removed from the suspend & resume functions: if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) @@ -184,8 +183,6 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv) gen9_disable_guc_interrupts(dev_priv); - ctx = dev_priv->kernel_context; - data[0] = INTEL_GUC_ACTION_ENTER_S_STATE; /* any value greater than GUC_POWER_D0 */ data[1] = GUC_POWER_D1; @@ -225,7 +222,6 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv) int intel_guc_resume(struct drm_i915_private *dev_priv) { struct intel_guc *guc = &dev_priv->guc; - struct i915_gem_context *ctx; u32 data[3]; if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) @@ -234,8 +230,6 @@ int intel_guc_resume(struct drm_i915_private *dev_priv) if (i915_modparams.guc_log_level >= 0) gen9_enable_guc_interrupts(dev_priv); - ctx = dev_priv->kernel_context; - data[0] = INTEL_GUC_ACTION_EXIT_S_STATE; data[1] = GUC_POWER_D0; data[2] = guc_ggtt_offset(guc->shared_data); diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c index 5cd9bc53e021..47c74ef0bd23 100644 --- a/drivers/gpu/drm/i915/intel_guc.c +++ b/drivers/gpu/drm/i915/intel_guc.c @@ -176,7 +176,6 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset) int intel_guc_suspend(struct drm_i915_private *dev_priv) { struct intel_guc *guc = &dev_priv->guc; - struct i915_gem_context *ctx; u32 data[3];