@@ -704,6 +704,16 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
else
tmp |= EOTP_DISABLED;
+ if (is_vid_mode(intel_dsi) && intel_dsi->blanking_packets_during_bllp)
+ tmp |= BLANKING_PACKET_ENABLE;
+ else
+ tmp &= BLANKING_PACKET_ENABLE;
+
+ if (intel_dsi->lp_clock_during_lpm)
+ tmp |= LP_CLOCK_DURING_LPM;
+ else
+ tmp &= LP_CLOCK_DURING_LPM;
+
/* enable link calibration if freq > 1.5Gbps */
if (afe_clk(encoder, pipe_config) >= 1500 * 1000) {
tmp &= ~LINK_CALIBRATION_MASK;
@@ -82,6 +82,8 @@ struct intel_dsi {
/* eot for MIPI_EOT_DISABLE register */
u8 eotp_pkt;
u8 clock_stop;
+ bool blanking_packets_during_bllp;
+ bool lp_clock_during_lpm;
u8 escape_clk_div;
u8 dual_link;
@@ -777,6 +777,8 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
+ intel_dsi->blanking_packets_during_bllp = mipi_config->blanking_packets_during_bllp;
+ intel_dsi->lp_clock_during_lpm = mipi_config->lp_clock_during_lpm;
intel_dsi->lane_count = mipi_config->lane_cnt + 1;
intel_dsi->pixel_format =
vbt_to_dsi_pixel_format(mipi_config->videomode_color_format);
Set the relevant DSI_TRANS_FUNC_CONF bits according to VBT DSI DPHY config. The DSI VBT usage is a nightmare, but that's for another time. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/icl_dsi.c | 10 ++++++++++ drivers/gpu/drm/i915/display/intel_dsi.h | 2 ++ drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 2 ++ 3 files changed, 14 insertions(+)