| Message ID | 20181116010412.23967-3-jarkko.sakkinen@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v17,01/23] x86/sgx: Update MAINTAINERS | expand |
On Fri, Nov 16, 2018 at 03:01:09AM +0200, Jarkko Sakkinen wrote: > From: Kai Huang <kai.huang@linux.intel.com> > > X86_FEATURE_SGX reflects whether or not the CPU supports Intel's > Software Guard eXtensions (SGX). > > Signed-off-by: Kai Huang <kai.huang@linux.intel.com> > Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com> > --- > arch/x86/include/asm/cpufeatures.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index 28c4a502b419..da7fed4939a3 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -236,6 +236,7 @@ > /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */ > #define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/ > #define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3B */ > +#define X86_FEATURE_SGX ( 9*32+ 2) /* Software Guard Extensions */ > #define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */ > #define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */ > #define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */ > -- Reviewed-by: Borislav Petkov <bp@suse.de>
On Fri, Nov 16, 2018 at 03:28:40PM +0100, Borislav Petkov wrote:
> Reviewed-by: Borislav Petkov <bp@suse.de>
Thank you, the very first reviewed-by 8-)
/Jarkko
On Fri, Nov 16, 2018 at 05:13:51PM +0200, Jarkko Sakkinen wrote: > On Fri, Nov 16, 2018 at 03:28:40PM +0100, Borislav Petkov wrote: > > Reviewed-by: Borislav Petkov <bp@suse.de> > > Thank you, the very first reviewed-by 8-) I will also add Sean as co-maintainer as he has the KVM angle and is needed to ack patches in the future. This functionality really needs two eyes. Has shown to have value in many occasions. /Jarkko
On Fri, Nov 16, 2018 at 05:18:45PM +0200, Jarkko Sakkinen wrote: > I will also add Sean as co-maintainer as he has the KVM angle and is > needed to ack patches in the future. This functionality really needs > two eyes. Has shown to have value in many occasions. Yap, two maintainers or a maintainer group for a bigger subsystem or arch is always much better than a single poor dude trying to cover it all.
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 28c4a502b419..da7fed4939a3 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -236,6 +236,7 @@ /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */ #define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/ #define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3B */ +#define X86_FEATURE_SGX ( 9*32+ 2) /* Software Guard Extensions */ #define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */ #define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */ #define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */