From patchwork Thu Jul 16 13:52:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jarkko Sakkinen X-Patchwork-Id: 11667457 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C81416C1 for ; Thu, 16 Jul 2020 13:53:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B7B2E20825 for ; Thu, 16 Jul 2020 13:53:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728093AbgGPNxp (ORCPT ); Thu, 16 Jul 2020 09:53:45 -0400 Received: from mga11.intel.com ([192.55.52.93]:48056 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726986AbgGPNxp (ORCPT ); Thu, 16 Jul 2020 09:53:45 -0400 IronPort-SDR: 5wX9w7WCQsvMGzSmK9p0H/m6QsfNquohN/AEjODJO+6oXCqmLNKEeS681xmbvfxQzrjTl0GzwU 3Dvgnh3E3TyA== X-IronPort-AV: E=McAfee;i="6000,8403,9683"; a="147368384" X-IronPort-AV: E=Sophos;i="5.75,359,1589266800"; d="scan'208";a="147368384" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jul 2020 06:53:44 -0700 IronPort-SDR: d/mYQX24GIFvWrFe0ojmopRlk2JfmMU2TdM3wve6JY9CRav7lpyy0beitzmo3shyRjfd04SBfB 5UUIU4O/hjUA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,359,1589266800"; d="scan'208";a="325150023" Received: from lettner-mobl.ger.corp.intel.com (HELO localhost) ([10.252.32.212]) by FMSMGA003.fm.intel.com with ESMTP; 16 Jul 2020 06:53:34 -0700 From: Jarkko Sakkinen To: x86@kernel.org, linux-sgx@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Sean Christopherson , Borislav Petkov , Jethro Beekman , Jarkko Sakkinen , akpm@linux-foundation.org, andriy.shevchenko@linux.intel.com, asapek@google.com, cedric.xing@intel.com, chenalexchen@google.com, conradparker@google.com, cyhanish@google.com, dave.hansen@intel.com, haitao.huang@intel.com, josh@joshtriplett.org, kai.huang@intel.com, kai.svahn@intel.com, kmoy@google.com, ludloff@google.com, luto@kernel.org, nhorman@redhat.com, npmccallum@redhat.com, puiterwijk@redhat.com, rientjes@google.com, tglx@linutronix.de, yaozhangx@google.com Subject: [PATCH v36 02/24] x86/cpufeatures: x86/msr: Add Intel SGX Launch Control hardware bits Date: Thu, 16 Jul 2020 16:52:41 +0300 Message-Id: <20200716135303.276442-3-jarkko.sakkinen@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200716135303.276442-1-jarkko.sakkinen@linux.intel.com> References: <20200716135303.276442-1-jarkko.sakkinen@linux.intel.com> MIME-Version: 1.0 Sender: linux-sgx-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sgx@vger.kernel.org From: Sean Christopherson Add X86_FEATURE_SGX_LC, which informs whether or not the CPU supports SGX Launch Control. Add MSR_IA32_SGXLEPUBKEYHASH{0, 1, 2, 3}, which when combined contain a SHA256 hash of a 3072-bit RSA public key. SGX backed software packages, so called enclaves, are always signed. All enclaves signed with the public key are unconditionally allowed to initialize. [1] Add FEAT_CTL_SGX_LC_ENABLED, which informs whether the aformentioned MSRs are writable or not. If the bit is off, the public key MSRs are read-only for the OS. If the MSRs are read-only, the platform must provide a launch enclave (LE). LE can create cryptographic tokens for other enclaves that they can pass together with their signature to the ENCLS(EINIT) opcode, which is used to initialize enclaves. Linux is unlikely to support the locked configuration because it takes away the control of the launch decisions from the kernel. [1] Intel SDM: 38.1.4 Intel SGX Launch Control Configuration Reviewed-by: Borislav Petkov Acked-by: Jethro Beekman Signed-off-by: Sean Christopherson Co-developed-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen Reviewed-by: Darren Kenny --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/msr-index.h | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 545ac3e0e269..0a4541e4f076 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -352,6 +352,7 @@ #define X86_FEATURE_CLDEMOTE (16*32+25) /* CLDEMOTE instruction */ #define X86_FEATURE_MOVDIRI (16*32+27) /* MOVDIRI instruction */ #define X86_FEATURE_MOVDIR64B (16*32+28) /* MOVDIR64B instruction */ +#define X86_FEATURE_SGX_LC (16*32+30) /* Software Guard Extensions Launch Control */ /* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */ #define X86_FEATURE_OVERFLOW_RECOV (17*32+ 0) /* MCA overflow recovery support */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 18e08da19f16..3d7c89a8533f 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -582,6 +582,7 @@ #define FEAT_CTL_LOCKED BIT(0) #define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1) #define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2) +#define FEAT_CTL_SGX_LC_ENABLED BIT(17) #define FEAT_CTL_SGX_ENABLED BIT(18) #define FEAT_CTL_LMCE_ENABLED BIT(20) @@ -602,6 +603,12 @@ #define MSR_IA32_UCODE_WRITE 0x00000079 #define MSR_IA32_UCODE_REV 0x0000008b +/* Intel SGX Launch Enclave Public Key Hash MSRs */ +#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C +#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D +#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E +#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F + #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b #define MSR_IA32_SMBASE 0x0000009e