Message ID | 20190918072329.1911-1-tao3.xu@intel.com (mailing list archive) |
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Headers | show
Return-Path: <SRS0=6oZb=XN=vger.kernel.org=kvm-owner@kernel.org> Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 35AEF16B1 for <patchwork-kvm@patchwork.kernel.org>; Wed, 18 Sep 2019 07:23:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1E6B7218AF for <patchwork-kvm@patchwork.kernel.org>; Wed, 18 Sep 2019 07:23:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728404AbfIRHXf (ORCPT <rfc822;patchwork-kvm@patchwork.kernel.org>); Wed, 18 Sep 2019 03:23:35 -0400 Received: from mga07.intel.com ([134.134.136.100]:60890 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726077AbfIRHXe (ORCPT <rfc822;kvm@vger.kernel.org>); Wed, 18 Sep 2019 03:23:34 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Sep 2019 00:23:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,519,1559545200"; d="scan'208";a="187694676" Received: from tao-optiplex-7060.sh.intel.com ([10.239.159.36]) by fmsmga007.fm.intel.com with ESMTP; 18 Sep 2019 00:23:32 -0700 From: Tao Xu <tao3.xu@intel.com> To: pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com, mtosatti@redhat.com Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, tao3.xu@intel.com, jingqi.liu@intel.com Subject: [PATCH RESEND v4 0/2] x86: Enable user wait instructions Date: Wed, 18 Sep 2019 15:23:27 +0800 Message-Id: <20190918072329.1911-1-tao3.xu@intel.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: <kvm.vger.kernel.org> X-Mailing-List: kvm@vger.kernel.org |
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x86: Enable user wait instructions
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